PCF85063TP datasheet(51/52 Pages) NXP

51 / 52 page

PCF85063TP

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Product data sheet

Rev. 4 — 6 May 2015

51 of 52

NXP Semiconductors

PCF85063TP

Tiny Real-Time Clock/calendar

27. Figures

Fig 1.

Block diagram of PCF85063TP . . . . . . . . . . . . . . .2

Fig 2.

Pin configuration for HWSON8 (PCF85063TP) . . .3

Fig 3.

Handling address registers . . . . . . . . . . . . . . . . . .4

Fig 4.

STOP bit functional diagram . . . . . . . . . . . . . . . . .8

Fig 5.

STOP bit release timing . . . . . . . . . . . . . . . . . . . . .9

Fig 6.

Software reset command . . . . . . . . . . . . . . . . . . .10

Fig 7.

INT example for MI . . . . . . . . . . . . . . . . . . . . . . . 11

Fig 8.

Offset calibration calculation workflow . . . . . . . . .16

Fig 9.

Result of offset calibration . . . . . . . . . . . . . . . . . .17

Fig 10. OS flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Fig 11. Data flow for the time function . . . . . . . . . . . . . . .21

Fig 12. Access time for read/write operations . . . . . . . . .22

Fig 13. Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Fig 14. Definition of START and STOP conditions. . . . . .23

Fig 15. System configuration . . . . . . . . . . . . . . . . . . . . . .24

Fig 16. Acknowledgement on the I2C-bus . . . . . . . . . . . .24

Fig 17. Master transmits to slave receiver

(WRITE mode) . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Fig 18. Master reads after setting register address

(WRITE register address; READ data) . . . . . . . .26

Fig 19. Device diode protection diagram of

PCF85063TP . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Fig 20. Typical IDD with respect to fSCL . . . . . . . . . . . . . .30

Fig 21. Typical IDD as a function of temperature . . . . . . .31

Fig 22. Typical IDD with respect to VDD . . . . . . . . . . . . . .32

Fig 23. IDD with respect to quartz RS . . . . . . . . . . . . . . . .33

Fig 24. Oscillator frequency variation with respect

to VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Fig 25. I2C-bus timing diagram; rise and fall times

refer to 30 % and 70 % . . . . . . . . . . . . . . . . . . . .35

Fig 26. Application diagram for PCF85063TP . . . . . . . . .36

Fig 27. Package outline SOT1069-2 (HWSON8) of

PCF85063TP . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Fig 28. Temperature profiles for large and small

components . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Fig 29. Footprint information for reflow soldering of

SOT1069-2 (HWSON8) of PCF85063TP . . . . . .42

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