APPLICATION INFORMATION

CONNECTION DIAGRAMS

SCK

24

23

22

21

20

19

18

17

16

15

5

6

7

8

9

10

11

12

13

14

PCM1680

DATA1

BCK

LRCK

VDD

DGND

DATA2

DATA3

DATA4

MSEL

AGND2

AGND1

VCC2

VOUT3

VOUT4

VOUT5

VCC1

VOUT7

VOUT6

ZERO1

1

2

3

4

MS/ADR

MC/SCL

MD/SDA

28

27

26

25

ZERO2

VOUT1

VOUT2

VCOM

VOUT8

µC or µP

Audio DSP

or

Decoder

R7

PLL170x

R6

R5

27-MHz

Master

Clock

R4

R2

R3

R1

C9

5 V Analog

0 V

C13

C1−C8: 4.7-µF to 10-µF Electrolytic Typical

C9−C11: 1-µF Ceramic Typical

C12, C13: 10-µF Electrolytic Typical

R1−R7: 22 Ω to 100 Ω Typical

+

C1

+

C2

+

C12

C11

C10

+

C3

+

C4

+

C5

+

C6

+

C7

+

C8

L

R

LF

RF

RS

LS

CTR

SUB

Output

Low-Pass

Filter

S0057-01

+

PCM1680

www.ti.com.................................................................................................................................................. SLES133B – MARCH 2005 – REVISED OCTOBER 2008

A basic connection diagram is shown in Figure 32, with the necessary power-supply bypassing and decoupling

components. Texas Instruments’ PLL170x is used to generate the system clock input at SCK, as well as

generating the clock for the audio signal processor. The use of series resistors (22

Ω to 100 Ω) is recommended

for SCK, LRCK, BCK, DATA1, DATA2, DATA3, and DATA4. The series resistor combines with the stray printed

circuit board (PCB) capacitance and device input capacitance to form a low-pass filter that removes

high-frequency noise from the digital signal, thus reducing high-frequency emission.

Figure 32. Basic Connection Diagram

Copyright © 2005–2008, Texas Instruments Incorporated

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