SYSCLK

0.8 V

2.0 V

tCLKIL

tCLKIH

T0005-03

RESET AND POWER DOWN

1024 System Clock Periods

Reset

Reset Removal

4.4 V

4.0 V

3.6 V

VCC / VDD

Internal Reset

System Clock

T0014-01

3 Clocks Minimum

PCM1800

www.ti.com ............................................................................................................................................... SBAS071B – OCTOBER 2000 – REVISED AUGUST 2008

Table 1. System Clock Frequencies

SAMPLING RATE FREQUENCY

SYSTEM CLOCK FREQUENCY (MHz)

(kHz)

256 fs

384 fs

512 fs

32

8.1920

12.2880

16.3840

44.1

11.2896

16.9344

22.5792

48

12.2880

18.4320

24.5760

System clock pulse duration, HIGH

t(CLKIH)

12 ns (min)

System clock pulse duration, LOW

t(CLKIL)

12 ns (min)

Figure 19. System Clock Timing

The PCM1800 has both an internal power-on reset circuit and an external forced reset (RSTB, pin 6). The

internal power-on reset initializes (resets) when the supply voltage (VCC/VDD) exceeds 4 V (typical). To initiate the

reset sequence externally, apply a logic-level LOW to the RSTB pin.

The RSTB pin is terminated by an internal pulldown resistor. If the RSTB pin is unconnected, the ADC remains in

the reset state. Because the system clock is used as the clock signal for the reset circuit, the system clock must

be supplied as soon as power is applied; more specifically, the device must receive at least three system clock

cycles before VDD > 4 V and RSTB = HIGH. If this system clock requirement cannot be assured in an application,

RSTB must be held LOW until the system clock is supplied. While VCC/VDD < 4 V (typical), RSTB = LOW, and for

1024 system clock periods after VCC/VDD > 4.0 V and RSTB = HIGH, the PCM1800 stays in the reset state and

the digital output is forced to zero. The digital output is valid 18,436 fS periods after release from the reset state.

During reset, the logic circuits and the digital filter stop operating and enter the power-down mode. Figure 20 and

Figure 21 illustrate the internal power-on reset and external reset timing.

Figure 20. Internal Power-On Reset Timing

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