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PCM1807PW Datasheet(PDF) 17 Page - Texas Instruments |
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PCM1807PW Datasheet(HTML) 17 Page - Texas Instruments |
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17 / 34 page ![]() www.ti.com BCK LRCK DOUT t(BCKH) t(BCKL) t(CKLR) t(LRCP) t(BCKP) t(CKDO) t(LRDO) 0.5 VDD 0.5 VDD 0.5 VDD T0018-02 BCK SCKI t(SCKBCK) 1.4 V 0.5 VDD T0074-01 t(SCKBCK) PCM1807 SLES147 – SEPTEMBER 2005 SYMBOL PARAMETER MIN TYP MAX UNIT t(BCKP) BCK period 150 1/(64 fS) 1000 ns t(BCKH) BCK pulse duration, HIGH 65 600 ns t(BCKL) BCK pulse duration, LOW 65 600 ns t(CKLR) Delay time, BCK falling edge to LRCK valid –10 20 ns t(LRCP) LRCK period 10 1/fS 65 µs t(CKDO) Delay time, BCK falling edge to DOUT valid –10 20 ns t(LRDO) Delay time, LRCK edge to DOUT valid –10 20 ns NOTE: Timing measurement reference level is 0.5 VDD. Load capacitance of all signals is 20 pF. Figure 23. Audio Data Interface Timing (Master Mode: LRCK and BCK Work as Outputs) SYMBOL PARAMETER MIN TYP MAX UNIT t(SCKBCK) Delay time, SCKI rising edge to BCK edge 5 30 ns NOTE: Timing measurement reference level is 1.4 V for input and 0.5 VDD for output. Load capacitance of BCK is 20 pF. This timing is applied when SCKI frequency is less than 25 MHz. Figure 24. Audio Clock Interface Timing (Master Mode: BCK Works as Output) 17 |
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