www.ti.com

MODE CONTROL REGISTERS

PCM3060

SLAS533B – MARCH 2007 – REVISED MARCH 2008

The PCM3060 has many user-programmable functions which are accessed via control registers, and they are

programmed through the SPI or I2C serial control port. Table 3 lists the available mode control functions along

with reset default conditions and associated register addresses. The register map is shown in Table 3.

Table 3. User-Programmable Mode Control Functions

FUNCTION RESET

DEFAULT

REGISTER

LABEL

Mode control register reset (ADC and DAC)

Normal operation

64

MRST

System reset (ADC and DAC)

Normal operation

64

SRST

ADC power-save control (ADC)

Power save

64

ADPSV

DAC power-save control (DAC)

Power save

64

DAPSV

VOUT configuration control (DAC)

Differential

64

S/E

Digital attenuation control, 0 dB to –100 dB in 0.5-dB steps

0 dB, no attenuation

65 and 66

AT21[7:0], AT22[7:0]

(DAC)

Clock select for DAC operation (DAC)

CLK2 enable

67

CSEL2

Master/slave mode for DAC audio interface (DAC)

Slave

67

M/S 2[2:0]

Interface format for DAC audio interface (DAC)

I2S

67

FMT2[1:0]

Oversampling rate control (DAC)

Low (x64/x32/x16)

68

OVER

Output phase select (DAC)

Normal

68

DREV2

Soft-mute control (DAC)

Mute disabled

68

MUT22, MUT21

Digital filter rolloff control (DAC)

Sharp rolloff

69

FLT

De-emphasis sampling rate selection (DAC)

44.1 kHz

69

DMF[1:0]

De-emphasis function control (DAC)

De-emphasis disabled

69

DMC

Zero-flag polarity control (DAC)

High for detection

69

ZREV

Zero-flag form select (DAC)

L-ch, R-ch independent

69

AZRO

Digital attenuation control, 20 dB to –100 dB in 0.5-dB steps

0 dB, no attenuation

70 and 71

AT11[7:0], AT12[7:0]

(ADC)

Clock select for ADC operation (ADC)

CLK1 enable

72

CSEL1

Master/slave mode for ADC audio interface (ADC)

Slave

72

M/S1[2:0]

Interface format for ADC audio interface (ADC)

I2S

72

FMT1[1:0]

Zero-cross detection disable for digital attenuation control (ADC)

Zero-cross detection enabled

73

ZCDD

HPF bypass control (ADC)

Bypass disabled

73

BYP

Input phase select (ADC)

Normal

73

DREV1

Soft-mute control (ADC)

Mute disabled

73

MUT12, MUT11

Table 4. Register Map

REGISTER ADDRESS

DATA

HEX

DEC

B15

B14

B13

B12

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

40h

Register 64

0

1

0

0

0

0

0

0

MRST

SRST

ADPSV

DAPSV

RSV

(1)

S/E

RSV

(1)

RSV

(1)

41h

Register 65

0

1

0

0

0

0

0

1

AT217

AT216

AT215

AT214

AT213

AT212

AT211

AT210

42h

Register 66

0

1

0

0

0

0

1

0

AT227

AT226

AT225

AT224

AT223

AT222

AT221

AT220

43h

Register 67

0

1

0

0

0

0

1

1

CSEL2

M/S 22

M/S 21

M/S 20

FMT21

FMT20

RSV

(1)

RSV

(1)

44h

Register 68

0

1

0

0

0

1

0

0

OVER

DREV2

MUT22

MUT21

RSV

(1)

RSV

(1)

RSV

(1)

RSV

(1)

45h

Register 69

0

1

0

0

0

1

0

1

FLT

DMF1

DMF0

DMC

ZREV

AZRO

RSV

(1)

RSV

(1)

46h

Register 70

0

1

0

0

0

1

1

0

AT117

AT116

AT115

AT114

AT113

AT112

AT111

AT110

47h

Register 71

0

1

0

0

0

1

1

1

AT127

AT126

AT125

AT124

AT123

AT122

AT121

AT120

48h

Register 72

0

1

0

0

1

0

0

0

CSEL1

M/S 12

M/S 11

M/S 10

FMT11

FMT10

RSV

(1)

RSV

(1)

49h

Register 73

0

1

0

0

1

0

0

1

ZCDD

BYP

DREV1

MUT12

MUT11

RSV

(1)

RSV

(1)

RSV

(1)

(1)

RSV means reserved for factory use or future extension, and these bits should be set to 0 during regular operation. Do not write any

values in addresses other than those listed.

Copyright © 2007–2008, Texas Instruments Incorporated

Submit Documentation Feedback

29

Product Folder Link(s): PCM3060