INPUT

OUTPUT

tf

tD1

tr

tD2

90%

10%

50%

50%

INPUT

OUTPUT

tr

tD1

tf

tD2

90%

10%

50%

50%

SM72482

www.ti.com

SNVS696C – JANUARY 2011 – REVISED APRIL 2013

Electrical Characteristics (continued)

TJ = −40°C to +125°C, VCC = 12V, VEE = 0V, No Load on OUT_A or OUT_B, unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Units

IIL

Input Current Low

IN_A=IN_B=VCC

−1

0.1

1

IIH

Input Current High

IN_A=IN_B=VCC(SM72482MY-1)

10

18

25

µA

IN_B=VCC (SM72482MA-4)

10

18

25

IN_A=VCC (SM72482MA-4)

-1

0.1

1

OUTPUT DRIVERS

ROH

Output Resistance High

IOUT = −10 mA

(1)

30

50

Ω

ROL

Output Resistance Low

IOUT = + 10 mA

(1)

1.4

2.5

Ω

ISource

Peak Source Current

OUTA/OUTB = VCC/2,

3

A

200 ns Pulsed Current

ISink

Peak Sink Current

OUTA/OUTB = VCC/2,

5

A

200 ns Pulsed Current

SWITCHING CHARACTERISTICS

td1

Propagation Delay Time Low to

CLOAD = 2 nF, see Figure 2 and

25

40

ns

High, IN rising (IN to OUT)

Figure 3

td2

Propagation Delay Time High to

CLOAD = 2 nF, see Figure 2 and

25

40

ns

Low, IN falling (IN to OUT)

Figure 3

tr

Rise Time

CLOAD = 2 nF, see Figure 2 and

14

25

ns

Figure 3

tf

Fall Time

CLOAD = 2 nF, see Figure 2 and

12

25

ns

Figure 3

LATCHUP PROTECTION

AEC - Q100, Method 004

TJ = 150°C

500

mA

THERMAL RESISTANCE

θJA

Junction to Ambient,

SOIC Package

170

°C/W

0 LFPM Air Flow

VSSOP Package

60

θJC

Junction to Case

SOIC Package

70

°C/W

VSSOP Package

4.7

(1)

The output resistance specification applies to the MOS device only. The total output current capability is the sum of the MOS and

Bipolar devices.

TIMING WAVEFORMS

Figure 2. Inverting

Figure 3. Non-Inverting

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