ISL85403EVAL2Z datasheet(21/25 Pages) RENESAS

21 / 25 page

ISL85403

FN8631 Rev.4.00

Page 21 of 24

Sep 28, 2020

Its transfer function is expressed as Equation 29:

where:

Compensator design goal:

Loop bandwidth fc:

Gain margin: >10dB

Phase margin: 45°

The compensator design procedure is as follows:

1. Position



CZ2 and CP to derive R

3 and C3.

Put the compensator zero



CZ2 at (1 to 3)/(R

oCo)

Put the compensator pole



CP at ESR zero or 0.35 to 0.5

times of switching frequency, whichever is lower. In an

all-ceramic-cap design, the ESR zero is normally higher than

half of the switching frequency. R3 and C3 can be derived as

follows:

Case A: ESR zero

less than (0.35 to 0.5)fSW

Case B: ESR zero

larger than (0.35 to 0.5)fSW

2. Derive R2 and C1.

The loop gain Lv(S) at crossover frequency of fc has unity

gain. Therefore, C1 is determined by Equation 35.

The compensator zero



CZ1 can boost the phase margin and

bandwidth. To put



CZ1 at two times of crossover frequency

fc is a good starting point. It can be adjusted according to the

specific design. R1 can be derived from Equation 36.

Example: VIN = 12V, Vo = 5V, Io = 2A, fSW = 500kHz,

Co = 60µF/3mΩ, L = 10µH, Rt = 0.20V/A, fc = 50kHz,

R1 = 105k, RBIAS =20kΩ.

Select the crossover frequency to be 35kHz. Because the

output capacitors are all ceramic, use Equations 33 and 34

to derive R3 to be 20k and C3 to be 470pF.

Then use Equations 35 and 36 to calculate C1 to be 180pF

and R2 to be 12.7k. Select 150pF for C1 and 15k for R2.

There is approximately 30pF parasitic capacitance between

COMP to FB pins that contributes to a high frequency pole. Any

extra external capacitor is not recommended between COMP and

FB.

Figure 34 shows the simulated Bode plot of the loop. It has

26kHz loop bandwidth with 70° phase margin and -28 dB gain

margin.

Note in applications where the PFM mode is required especially

when type III compensation network is used, the value of the

capacitor between the COMP pin and the FB pin (not the

capacitor in series with the resistor between COMP and FB)

should be minimal to reduce the noise coupling for proper PFM

operation. No external capacitor between COMP and FB is

recommended for PFM applications.

In PFM mode operations, an RC filter from FB to ground (R in

series with C, connecting from FB to ground) can help reduce the

noise effects injected to FB pin. The recommended values for the

filter are 499Ω to 1k for the R and 470pF for the C.

Av S



vˆcomp

vˆO

-----------------

SR1C1

-------------------



cz1

-------------



 1



cz2

-------------







----------





---------------------------------------------------------

(EQ. 29)



cz1

R2C1

---------------



cz2

R1 R3

C

----------------------------------





R3C3

---------------

---to 1

------



 f



cz2

RoCo

---------------

(EQ. 30)

R

cCo

----------------------

RoCo 3RcCo

–

3R1

----------------------------------------

(EQ. 31)

3RcR1

Ro 3Rc

–

------------------------

(EQ. 32)

R

cCo

----------------------

0.33RoCofSW 0.46

–

fSWR1

--------------------------------------------------------

(EQ. 33)

0.73RoCofs 1

–

-----------------------------------------

(EQ. 34)

R1 R3

C

f

cRtR1Co

----------------------------------

(EQ. 35)

f

cC1

--------------------

(EQ. 36)

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