STM32F205ZET6VTR datasheet(21/184 Pages) STMICROELECTRONICS

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STM32F20xxx

Functional overview

183

Functional overview

3.1

ARM® Cortex®-M3 core with embedded Flash and SRAM

The ARM® Cortex®-M3 processor is the latest generation of ARM processors for embedded

systems. It was developed to provide a low-cost platform that meets the needs of MCU

implementation, with a reduced pin count and low-power consumption, while delivering

outstanding computational performance and an advanced response to interrupts.

The ARM® Cortex®-M3 32-bit RISC processor features exceptional code-efficiency,

delivering the high-performance expected from an ARM core in the memory size usually

associated with 8- and 16-bit devices.

With its embedded ARM® core, the STM32F20x family is compatible with all ARM® tools

and software.

Figure 4 shows the general block diagram of the STM32F20x family.

3.2

Adaptive real-time memory accelerator (ART Accelerator™)

The ART Accelerator™ is a memory accelerator which is optimized for STM32 industry-

standard ARM® Cortex®-M3 processors. It balances the inherent performance advantage of

the ARM® Cortex®-M3 over Flash memory technologies, which normally requires the

processor to wait for the Flash memory at higher operating frequencies.

To release the processor full 150 DMIPS performance at this frequency, the accelerator

implements an instruction prefetch queue and branch cache which increases program

execution speed from the 128-bit Flash memory. Based on CoreMark® benchmark, the

performance achieved thanks to the ART accelerator is equivalent to 0 wait state program

execution from Flash memory at a CPU frequency up to 120 MHz.

3.3

Memory protection unit

The memory protection unit (MPU) is used to manage the CPU accesses to memory to

prevent one task to accidentally corrupt the memory or resources used by any other active

task. This memory area is organized into up to 8 protected areas that can in turn be divided

up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4

gigabytes of addressable memory.

The MPU is especially helpful for applications where some critical or certified code has to be

protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-

time operating system). If a program accesses a memory location that is prohibited by the

MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can

dynamically update the MPU area setting, based on the process to be executed.

The MPU is optional and can be bypassed for applications that do not need it.

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