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SN74LVC2G32

SCES201N – APRIL 1999 – REVISED SEPTEMBER 2015

SN74LVC2G32 Dual 2-Input Positive-OR Gate

1 Features

3 Description

This dual 2-input positive-OR gate is designed for

1

•

Available in the Texas Instruments

1.65-V to 5.5-V VCC operation.

NanoFree™ Package

The SN74LVC2G32 device performs the Boolean

•

Supports 5-V VCC Operation

function

in positive logic.

•

Inputs Accept Voltages to 5.5 V

•

Maximum tpd of 3.8 ns at 3.3 V

NanoFree

package

technology

is

a

major

breakthrough in IC packaging concepts, using the die

•

Low Power Consumption, 10-µA Maximum ICC

as the package.

•

±24-mA Output Drive at 3.3 V

This device is fully specified for partial-power-down

•

Typical VOLP (Output Ground Bounce)

applications using Ioff. The Ioff circuitry disables the

<0.8 V at VCC = 3.3 V, TA = 25°C

outputs,

preventing

damaging

current

backflow

•

Typical VOHV (Output VOH Undershoot)

through the device when it is powered down.

>2 V at VCC = 3.3 V, TA = 25°C

Device Information(1)

•

Ioff Supports Live Insertion, Partial-Power-Down

Mode, and Back-Drive Protection

PART NUMBER

PACKAGE

BODY SIZE

SN74LVC2G32DCT

SSOP (8)

2.95 mm × 2.80 mm

•

Can Be Used as a Down Translator to Translate

Inputs From a Maximum of 5.5 V Down to the VCC

SN74LVC2G32DCU

VSSOP (8)

2.30 mm × 2.00 mm

Level

SN74LVC2G32YZP

DSBGA (8)

1.91 mm × 0.91 mm

•

Latch-Up Performance Exceeds 100 mA Per

(1) For all available packages, see the orderable addendum at

JESD 78, Class II

the end of the data sheet.

•

ESD Protection Exceeds JESD 22

–

2000-V Human Body Model (A114-A)

–

1000-V Charged-Device Model (C101)

2 Applications

•

Down Translation

•

Logical OR

Logic Diagram (Positive Logic)

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.