74VHC74 datasheet(1/10 Pages) STMICROELECTRONICS

Part #	74VHC74

Description	DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR

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Manufacturer	STMICROELECTRONICS [STMicroelectronics]

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74VHC74

DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR

June 1999

s

HIGH SPEED:

fMAX =170 MHz (TYP.) at VCC =5V

s

LOW POWER DISSIPATION:

ICC =2

µA (MAX.) at TA =25 oC

s

HIGH NOISE IMMUNITY:

VNIH =VNIL =28% VCC (MIN.)

s

POWER DOWN PROTECTION ON INPUTS

s

SYMMETRICAL OUTPUT IMPEDANCE:

|IOH|=IOL = 8 mA (MIN)

s

BALANCED PROPAGATION DELAYS:

tPLH

≅ tPHL

s

OPERATING VOLTAGE RANGE:

VCC (OPR) = 2V to 5.5V

s

PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 74

s

IMPROVED LATCH-UP IMMUNITY

DESCRIPTION

The 74VHC74 is an advanced high-speed CMOS

DUAL D-TYPE FLIP FLOP WITH PRESET AND

CLEAR fabricated with sub-micron silicon gate

and

double-layer

metal

wiring

C

2MOS

technology.

A signal on the D INPUT is transfered to the Q

OUTPUT during the positive going transition of

the clock pulse.

CLEAR and PRESET are independent of the

clock and accomplished by a low setting on the

appropriate input.

It is ideal for low power applications maintaining

high speed operation similar to equivalent Bipolar

Schottky TTL.

Power down protection is provided on all inputs

and 0 to 7V can be accepted on inputs with no

regard to the supply voltage. This device can be

used to interface 5V to 3V.

All inputs

and

outputs are

equipped with

protection circuits against static discharge, giving

them 2KV ESD immunity and transient excess

voltage.

PIN CONNECTION AND IEC LOGIC SYMBOLS

ORDER CODES :

74VHC74M

74VHC74T

M

(Micro Package)

T

(TSSOP Package)

®

1/10

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