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LF3312 Datasheet(PDF) 21 Page - LOGIC Devices Incorporated |
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LF3312 Datasheet(HTML) 21 Page - LOGIC Devices Incorporated |
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21 / 33 page ![]() Configuration Register Definitions DEVICES INCORPORATED LF3312 12-Mbit Frame Buffer / FIFO Preliminary Datasheet LOGIC Devices Incorporated August 8, 2006 LDS.3312 O Video Imaging Product 21 Register 9[7:6] = TRS_SYNC[1:0] - response to embedded TRS EAV (a) 00 disable TRS sync detection (dflt) 01 F-bit of embedded TRS EAV marks current write pointer. 10 F-bit of embedded TRS EAV sets current write pointer to value set by BOUT/BIN or ALAT (1-chnl.modes) or ALAT & BLAT (2-chnl. modes, respectively). 11 F-bit of embedded TRS EAV clears current write pointer. - If B_FLD = 0 (frame-based sync), action is on each B-channel EAV with F = 0 for which the preceding EAV had F = 1. - If B_FLD = 1 (field-based sync), action is on each B-chan EAV whose F differs from that of the preceding EAV. A_FLD affects the tA-channel operation in the same fashion. Register 9[5] = B_FLD frame/field sync select, chnl B 0 use only falling F-bit in EAV; ignore rising (dflt) 1 use both rising and falling F-bit in EAV Register 9[4] = A_FLD frame/field sync select, chnl A 0 use only falling F-bit in EAV; ignore rising (dflt) 1 use both rising and falling F-bit in EAV Register 9[3] MARK_SEL - This signal is used in combination with pin BCLR to determine to effect of bringing RSET low on the read pointer(s). When RSET goes to 0: 0 force read pointer(s) to marked address(es) (dflt) 1 force read pointer(s) as shown in following table: OPMODE BCLR Read Pointer Equals: 0-3 1 BIN/BOUT address 0-3 0 BLAT address 4-7 x Ch. A=ALAT, Ch. B=BLAT |
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