PIC24FJ256GA705-ISLASHM4. datasheet(401/412 Pages) MICROCHIP

401 / 412 page

 2016 Microchip Technology Inc.

DS30010118B-page 401

PIC24FJ256GA705 FAMILY

INDEX

A/D

Achieving Maximum Performance ............................ 291

Control Registers ...................................................... 290

Extended DMA Operations ....................................... 289

Operation .................................................................. 287

Transfer Functions

10-Bit ................................................................ 307

12-Bit ................................................................ 306

AC Characteristics

A/D Conversion Timing Requirements...................... 374

A/D Specifications..................................................... 373

and Timing Parameters............................................. 368

Capacitive Loading on Output Pins........................... 368

CLKO and I/O Timing Requirements ........................ 371

External Clock Timing Requirements........................ 369

Internal RC Accuracy ................................................ 370

Load Conditions for Device Timing ........................... 368

Phase-Locked Loop Mode Specifications................. 370

RC Oscillator Start-up Time ...................................... 370

Reset and Brown-out Reset Requirements .............. 372

Analog/Digital Pins Configuration During ICSP .................. 34

Assembler

MPASM Assembler................................................... 346

Block Diagrams

12-Bit A/D Converter................................................. 288

12-Bit A/D Converter Analog Input Model................. 305

16-Bit Asynchronous Timer3..................................... 163

16-Bit Synchronous Timer2 ...................................... 163

16-Bit Timer1 Module................................................ 159

32-Bit Timer Mode .................................................... 186

Access Program Memory Using

Table Instructions ............................................... 60

Addressing for Table Registers................................... 71

Buffer Address Generation in PIA Mode................... 292

CALL Stack Frame...................................................... 57

CLCx Input Source Selection.................................... 279

CLCx Logic Function Combinatorial Options ............ 278

CLCx Module ............................................................ 277

Comparator Voltage Reference ................................ 315

Conceptual MCCPx Module...................................... 183

CPU Programmer’s Model .......................................... 37

CRC Module ............................................................. 271

CRC Shift Engine Detail............................................ 271

CTMU Connections and Internal Configuration

for Capacitance Measurement.......................... 318

CTMU Typical Connections and Internal

Configuration for Pulse Delay Generation ........ 319

CTMU Typical Connections and Internal

Configuration for Time Measurement ............... 319

Data Access from Program Space

Address Generation............................................ 59

DMA Module ............................................................... 63

Dual 16-Bit Timer Mode ............................................ 185

EDS Address Generation for Read Operations .......... 55

EDS Address Generation for Write Operations .......... 56

High/Low-Voltage Detect (HLVD)............................. 327

I2Cx Module ............................................................. 222

Individual Comparator Configurations,

CREF = 0.......................................................... 310

Individual Comparator Configurations,

CREF = 1, CVREFP = 0................................... 310

Individual Comparator Configurations,

CREF = 1, CVREFP = 1................................... 311

Input Capture x Module .................................... 167, 188

MCLR Pin Connection Example ................................. 30

On-Chip Regulator Connections............................... 341

Oscillator Circuit Placement ....................................... 33

Output Compare x (16-Bit Mode) ............................. 174

Output Compare x (Double-Buffered,....................... 176

Output Compare x Module ....................................... 187

PIC24F CPU Core ...................................................... 36

PIC24FJ256GA705 Family (General)......................... 19

PLL Module .............................................................. 108

PSV Operation (Lower Word)..................................... 62

PSV Operation (Upper Word)..................................... 62

Recommended Minimum Connections....................... 29

Reset System ............................................................. 79

RTCC Module........................................................... 252

Shared I/O Port Structure ......................................... 125

SPIx Master, Frame Master Connection .................. 219

SPIx Master, Frame Slave Connection .................... 220

SPIx Master/Slave Connection

(Enhanced Buffer Modes)................................. 218

SPIx Master/Slave Connection

(Standard Mode)............................................... 217

SPIx Module (Enhanced Mode)................................ 203

SPIx Slave, Frame Master Connection .................... 220

SPIx Slave, Frame Slave Connection ...................... 220

System Clock.............................................................. 97

Timer Clock Generator ............................................. 184

Timer2/3 (32-Bit)....................................................... 162

Triple Comparator Module........................................ 309

UARTx (Simplified) ................................................... 230

Watchdog Timer (WDT)............................................ 343

C Compilers

MPLAB C18.............................................................. 346

Capture/Compare/PWM/Timer

Auxiliary Output ........................................................ 189

General Purpose Timer ............................................ 185

Input Capture Mode.................................................. 188

Output Compare Mode ............................................. 186

Synchronization Sources.......................................... 193

Time Base Generator ............................................... 184

Capture/Compare/PWM/Timer (MCCP) ........................... 183

Charge Time Measurement Unit. See CTMU.

CLC

Control Registers...................................................... 280

Module-Specific Input Sources................................. 283

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