TPIC6C596

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SLIS093D – MARCH 2000 – REVISED MARCH 2015

8.3 Feature Description

8.3.1 Serial-In Interface

The TPIC6C596 device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage

register. Data transfers through both the shift and storage registers on the rising edge of the shift register clock

(SRCK) and the register clock (RCK), respectively. The storage register transfers data to the output buffer when

shift register clear (CLR) is high.

8.3.2 Clear Register

A logical low on CLR clears all registers in the device. TI suggests clearing the device during power up or

initialization.

8.3.3 Output Control

Holding the output enable (G) high holds all data in the output buffers low, and all drain outputs are off. Holding

G low makes data from the storage register transparent to the output buffers. When data in the output buffers is

low, the DMOS transistor outputs are off. When data is high, the DMOS transistor outputs are capable of sink-

current. This pin can also be used for global PWM dimming.

8.4 Device Functional Modes

8.4.1 Operation With V(VIN) < 4.5 V (Minimum V(VIN))

This device works normally during 4.5 V

≤ V(VIN) ≤ 5.5 V, when operation voltage is lower than 4.5 V. The

behavior of device can't be ensured, including communication interface and current capability.

8.4.2 Operating With 5.5 V < V(VIN) < 6 V

This device works normally during this voltage range, but reliability issues may occurs while the device works for

a long time in this voltage range.

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