ATTINY15_01 datasheet(21/79 Pages) ATMEL

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ATtiny15L

1187D–12/01

The Timer/Counter Interrupt

Flag Register – TIFR

• Bit 7 – Res: Reserved Bit

This bit is a reserved bit in the ATtiny15L and always reads as zero.

• Bit 6 – OCF1A: Output Compare Flag 1A

The OCF1A bit is set (one) when compare match occurs between Timer/Counter1 and

the data value in OCR1A (Output Compare Register 1A). OCF1A is cleared by hard-

ware when executing the corresponding interrupt handling vector. Alternatively, OCF1A

is cleared by writing a logical “1” to the flag. When the I-bit in SREG, OCIE1A, and

OCF1A are set (one), the Timer/Counter1 compare match A interrupt is executed.

• Bits 5..3 – Res: Reserved bits

These bits are reserved bits in the ATtiny15L and always read as zero.

• Bit 2 – TOV1: Timer/Counter1 Overflow Flag

The bit TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared

by hardware when executing the corresponding interrupt handling vector. Alternatively,

TOV1 is cleared by writing a logical “1” to the flag. When the SREG I-bit, TOIE1

(T i m er /Counter 1 O v erfl ow Inte rr upt Enabl e) and T OV 1 ar e s e t ( one ), the

Timer/Counter1 Overflow interrupt is executed.

• Bit 1 – TOV0: Timer/Counter0 Overflow Flag

The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared

by hardware when executing the corresponding interrupt handling vector. Alternatively,

TOV0 is cleared by writing a logical “1” to the flag. When the SREG I-bit, TOIE0

(T i m er /Counter 0 O v erfl ow Inte rr upt Enabl e) and T OV 0 ar e s e t ( one ), the

Timer/Counter0 Overflow interrupt is executed.

• Bit 0 – Res: Reserved Bit

This bit is a reserved bit in the ATtiny15L and always reads as zero.

External Interrupt

The external interrupt is triggered by the INT0 pin. Observe that, if enabled, the interrupt

will trigger even if the INT0 pin is configured as an output. This feature provides a way of

generating a software interrupt. The external interrupt can be triggered by a falling or ris-

ing edge, a pin change, or a low level. This is set up as indicated in the specification for

the MCU Control Register (MCUCR). When the external interrupt is enabled and is con-

figured as level-triggered, the interrupt will trigger as long as the pin is held low.

The external interrupt is set up as described in the specification for the MCU Control

Pin Change Interrupt

The pin change interrupt is triggered by any change in logical value on any input or I/O

pin. Change on pins PB4..0 will always cause an interrupt. Change on pin PB5 will

cause an interrupt if the pin is configured as input or I/O, as described in the section “Pin

Descriptions” on page 4. Observe that, if enabled, the interrupt will trigger even if the

changing pin is configured as an output. This feature provides a way of generating a

software interrupt. Also observe that the pin change interrupt will trigger even if the pin

activity triggers another interrupt, for example the external interrupt. This implies that

one external event might cause several interrupts. The values on the pins are sampled

before detecting edges. If pin change interrupt is enabled, pulses that last longer than

Bit

7654

321

$38

–

OCF1A

––

–

TOV1

TOV0

–

TIFR

Read/Write

R/W

Initial Value

0000

000

ATTINY15 Datasheet(PDF) 21 Page - ATMEL Corporation

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