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IOV

DD AND VOLTAGE TRANSLATORS

DRIVING RESISTIVE AND CAPACITIVE LOADS

CROSSTALK

OUTPUT VOLTAGE STABILITY

SETTLING TIME AND OUTPUT GLITCH PERFORMANCE

DAC6573

SLAS402 – NOVEMBER 2003

IOVDD pin powers the digital input structures of the DAC6573. For single-supply operation, IOVDD can be tied to

VDD. For dual-supply operation, the IOVDD pin provides interface flexibility with various CMOS logic famil-

ies—connect it to the logic supply of the system. Analog circuits and internal logic of the DAC6573 use VDD as

the supply voltage. The external logic high inputs get translated to VDD by level shifters. These level shifters use

the IOVDD voltage as a reference to shift the incoming logic HIGH levels to VDD. IOVDD operates from 2.7 V to 5.5

V regardless of the VDD voltage, ensuring compatibility with various logic families. Although specified down to 2.7

V, IOVDD operates as low as 1.8 V with degraded timing and temperature performance. For lowest power

consumption, ensure that logic VIH levels are as close as possible to IOVDD, and logic VIL levels as close as

possible to GND voltages.

The DAC6573 output stage is capable of driving loads of up to 1000 pF while remaining stable. Within the offset

and gain error margins, the DAC6573 can operate rail-to-rail when driving a capacitive load. Resistive loads of 2

k

Ω can be driven by the DAC6573 while achieving a good load regulation. When the outputs of the DAC are

driven to the positive rail under resistive loading, the PMOS transistor of each Class-AB output stage can enter

into the linear region. When this occurs, the added IR voltage drop deteriorates the linearity performance of the

DAC. This only occurs within approximately the top 20 mV of the DAC's digital input-to-voltage output transfer

characteristic. The reference voltage applied to the DAC6573 may be reduced below the supply voltage applied

to VDD in order to eliminate this condition if good linearity is a requirement at full scale (under resistive loading

conditions).

The DAC6573 architecture uses separate resistor strings for each DAC channel in order to achieve ultra-low

crosstalk performance. DC crosstalk seen at one channel during a full-scale change on the neighboring channel

is typically less than 0.01 LSBs. The ac crosstalk measured (for a full-scale, 1-kHz sine wave output generated at

one channel, and measured at the remaining output channel) is typically under -100 dB.

The DAC6573 exhibits excellent temperature stability of

±3 ppm/°C typical output voltage drift over the specified

temperature range of the device. This enables the output voltage of each channel to stay within a

±25-µV window

for a

±1°C ambient temperature change. Combined with good dc noise performance and true 10-Bit differential

linearity, the DAC6573 becomes a perfect choice for closed-loop control applications.

Settling time to within the 10-bit accurate range of the DAC6573 is achievable within 7 µs for a full-scale code

change at the input. Worst case settling times between consecutive code changes is typically less than 2 µs. The

high-speed serial interface of the DAC6573 is designed in order to support up to 188-kSPS update rate. For

full-scale output swings, the output stage of each DAC6573 channel typically exhibits less than 100 mV of

overshoot and undershoot when driving a 200 pF capacitive load. Code-to-code change glitches are extremely

low (~10 µV) given that the code-to-code transition does not cross an Nx64 code boundary. Due to internal

segmentation of the DAC6573, code-to-code glitches occur at each crossing of an Nx64 code boundary. These

glitches can approach 100 mVs for N = 15, but settle out within ~2 µs.

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