LM2611

SNOS965J – JUNE 2001 – REVISED DECEMBER 2015

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10 Layout

10.1 Layout Guidelines

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Connection between L1 and SW pin should be kept as short as possible to minimize inductance

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Connection between CCUK and SW should also be kept short

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The feedback resistor should be placed close to the NFB pin to minimize the path of the higher impedance

feedback node

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The feedback trace leading from Vout to the output to the feedback resistors should not pass under the

switch node between L1 and CCUK and the switch node between CCUK, L2 and D

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The feedback trace leading from Vout to the output to the feedback resistors should not pass under the

inductors L1 and L2

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A bypass capacitor CBYP of 0.1 µF should be placed close to VIN and GND pin

10.2 Layout Example

Figure 36. Example Layout Top

Figure 37. Example Layout Bottom

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