LM3565

SNVS957 – JANUARY 2013

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Capacitor Selection

The LM3565 requires 3 external capacitors for proper operation (CIN = 10 µF recommended (4.7 µF min) and 2 ×

COUT = 10 µF ). An additional 0.1 µF input capacitor placed right next to the VIN pin is recommended. Surface-

mount multi-layer ceramic capacitors are recommended. These capacitors are small, inexpensive, and have very

low equivalent series resistance (ESR <20 m

Ω typ.). Tantalum capacitors, OS-CON capacitors, and aluminum

electrolytic capacitors are not recommended for use with the LM3565 due to their high ESR, as compared to

ceramic capacitors.

For most applications, ceramic capacitors with X7R or X5R temperature characteristic are preferred for use with

the LM3565. These capacitors have tight capacitance tolerance (as good as ±10%) and hold their value over

temperature (X7R: ±15% over

−55°C to 125°C; X5R: ±15% over −55°C to 85°C).

Capacitors with Y5V or Z5U temperature characteristic are generally not recommended for use with the LM3565.

Capacitors with these temperature characteristics typically have wide capacitance tolerance (+80%,

−20%) and

vary significantly over temperature (Y5V: +22%,

−82% over −30°C to +85°C range; Z5U: +22%, −56% over

+10°C to +85°C range). Under some conditions, a nominal 1µF Y5V or Z5U capacitor could have a capacitance

of only 0.1 µF. Such detrimental deviation is likely to cause Y5V and Z5U capacitors to fail to meet the minimum

capacitance requirements of the LM3565.

The recommended voltage rating for the input capacitor is 10V (min = 6.3V). The recommended output capacitor

voltage rating is 16V (min = 10V). The recommended value takes into account the DC bias capacitance losses,

while the minimum rating takes into account the OVP trip levels.

Layout Considerations

The DSBGA is a chip-scale package with good thermal properties. For more detailed instructions on handling

and mounting DSBGA packages, refer to Texas Instruments Application Note AN-1112.

The high switching frequencies and large peak currents make the PCB layout a critical part of the design. The

proceeding steps must be followed to ensure stable operation and proper current source regulation.

1. Connect the inductor as close as possible to the SW pin. This reduces the inductance and resistance of the

switching node which minimizes ringing and excess voltage drops.

2. Connect the return terminals of the input capacitor and the output capacitor as close as possible to the

PGND pins and through low impedance traces.

3. Bypass VIN with a 10 µF ceramic capacitor and an additional 0.1 µF ceramic capacitor. Connect the positive

terminal of this capacitor as close as possible to VIN.

4. Connect COUT as close as possible to the VOUT pin. This reduces the inductance and resistance of the output

bypass node which minimizes ringing and voltage drops. This will improve efficiency and decrease the noise

injected into the current sources.

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Product Folder Links: LM3565