VCOM

COLUMN

LINE

R

R

R

R

R

C

C

C

C

C

LM6584

www.ti.com

SNOSA44C – MAY 2003 – REVISED MARCH 2013

Figure 27 is a simplified block diagram of a TFT display, showing how individual pixels are connected to the row,

column, and VCOM lines. Each pixel is represented by capacitor with an NMOS transistor connected to its top

plate. Pixels in a TFT panel are arranged in rows and columns. Row lines are connected to the NMOS gates,

and column lines to the NMOS sources. The back plate of every pixel is connected to a common voltage called

VCOM. Pixel brightness is controlled by voltage applied to the top plates, and the Column Drivers supply this

voltage via the column lines. Column Drivers ‘write’ this voltage to the pixels one row at a time, and this is

accomplished by having the Row Drivers select an individual row of pixels when their voltage levels are

transmitted by the Column Drivers. The Row Drivers sequentially apply a large positive pulse (typically 25V to

35V) to each row line. This turns-on NMOS transistors connected to an individual row, allowing voltages from the

column lines to be transmitted to the pixels.

VCOM DRIVER

The VCOM driver supplies a common voltage (VCOM) to all the pixels in a TFT panel. VCOM is a constant DC

voltage that lies in the middle of the column drivers’ output voltage range. As a result, when the column drivers

write to a row of pixels, they apply voltages that are either positive or negative with respect to VCOM. In fact, the

polarity of a pixel is reversed each time its row is selected. This allows the column drivers to apply an alternating

voltage to the pixels rather than a DC signal, which can ‘burn’ a pattern into an LCD display.

When column drivers write to the pixels, current pulses are injected onto the VCOM line. These pulses result from

charging stray capacitance between VCOM and the column lines (see Figure 27), which ranges typically from

16pF to 33pF per column. Pixel capacitance contributes very little to these pulses because only one pixel at a

time is connected to a column, and the capacitance of a single pixel is on the order of only 0.5pF. Each column

line has a significant amount of series resistance (typically 2k

Ω to 40kΩ), so the stray capacitance is distributed

along the entire length of a column. This can be modeled by the multi-segment RC network shown in Figure 28.

The total capacitance between VCOM and the column lines can range from 25nF to 100nF, and charging this

capacitance can result in positive or negative current pulses of 100mA, or more. In addition, a similar distributed

capacitance of approximately the same value exists between VCOM and the row lines. Therefore, the VCOM

driver’s load is the sum of these distributed RC networks with a total capacitance of 50nF to 200nF, and this load

can modeled like the circuit in Figure 28.

Figure 28. Model of Impedance between VCOM and Column Lines

A VCOM driver is essentially a voltage regulator that can source and sink current into a large capacitive load. To

simplify the analysis of this driver, the distributed RC network of Figure 28 has been reduced to a single RC load

in Figure 29. This load places a large capacitance on the VCOM driver output, resulting in an additional pole in the

op amp’s feedback loop. However, the op amp remains stable because CLOAD and RESR create a zero that

cancels the effect of this pole. The range of CLOAD is 50nF to 200nF and RESR is 20Ω to 100Ω, so this zero will

have a frequency in the range of 8KHz to160KHz, which is much lower than the gain bandwidth of most op

amps. As a result, the VCOM load adds very little phase lag when op amp loop gain is unity, and this allows the

VCOM Driver to remain stable. This was verified by measuring the small-signal bandwidth of the LM6584 with the

RC load of Figure 29. When driving an RC load of 50nF and 20

Ω, the LM6584 has a unity gain frequency of

6.12MHz with 41.5°C of phase margin. If the load capacitor is increased to 200nF and the resistance remains

20

Ω, the unity gain frequency is virtually unchanged: 6.05MHz with 42.9°C of phase margin.

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