Sync_Dmin

J1 -

fnom

fsync

LM26003, LM26003-Q1

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SNVS576F – AUGUST 2008 – REVISED FEBRUARY 2015

Feature Description (continued)

The switching frequency can also be synchronized to an external clock signal using the SYNC pin. The SYNC

pin allows the operating frequency to be varied above and below the nominal frequency setting. The adjustment

range is from 30% above nominal to 20% below nominal. External synchronization requires a 1.23-V minimum

(typical) peak signal level at the SYNC pin. The FREQ resistor must always be connected to initialize the nominal

operating frequency. The operating frequency is synchronized to the falling edge of the SYNC input. When

SYNC goes low, the high-side switch turns on. This allows any duty-cycle to be used for the sync signal when

synchronizing to a frequency higher than nominal. When synchronizing to a lower frequency, however, there is a

minimum duty-cycle requirement for the SYNC signal, given in the equation below:

where

•

fnom is the nominal switching frequency set by the FREQ resistor

•

fsync is a square wave.

(5)

If the SYNC pin is not used, it must be pulled low for normal operation. A 10 k

Ω pulldown resistor is

recommended to protect against a missing sync signal. Although the LM26003 device is designed to operate at

up to 500 kHz, maximum load current may be limited at higher frequencies due to increased temperature rise.

See the Thermal Considerations and TSD section.

8.3.5 VBIAS

The VBIAS pin is used to bypass the internal regulator which provides the bias voltage to the LM26003 device.

When the VBIAS pin is connected to a voltage greater than 3 V, the internal regulator automatically switches

over to the VBIAS input. This reduces the current into VIN (Iq) and increases system efficiency. Using the VBIAS

pin has the added benefit of reducing power dissipation within the device.

For most applications where 3 V < Vout < 10 V, VBIAS can be connected to VOUT. If not used, VBIAS should be

tied to GND.

If VBIAS drops below 2.9 V (typical), the device automatically switches over to supply the internal bias voltage

from Vin.

When the LM26003 device is powered with the circuit's output voltage through VBIAS, especially at low output

voltages such as 3.3 V, output ripple noise can couple in through the Vbias pin causing some falling edge jitter

on the switch node. To avoid this, additional bypassing close to the VBIAS pin with a low ESR capacitor can be

implemented. The circuit diagram in Figure 16 shows this bypass capacitor C8.

8.3.6 Low VIN Operation and UVLO

The LM26003 device is designed to remain operational during short line transients when the input voltage may

drop as low as 3.0 V. Minimum nominal operating input voltage is 4.0 V. Below this voltage, switch RDS(ON)

increases, due to the lower gate drive voltage from VDD. The minimum voltage required at VDD is approximately

3.5 V for normal operation within specification.

VDD can also be used as a pullup voltage for functions such as PGOOD and FPWM. Note that if VDD is used

externally, the pin is not recommended for loads greater than 1 mA.

If the input voltage approaches the nominal output voltage, the duty-cycle is maximized to hold up the output

voltage. In this mode of operation, once the duty-cycle reaches its maximum, the LM26003 device can skip a

maximum of seven off pulses, effectively increasing the duty-cycle and thus minimizing the dropout from input to

output. Typical off-pulse skipping waveforms are shown in Figure 13.

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