1

2

7

1A

1B

1Y

5

6

3

2A

2B

2Y

SN74LVC2G32-Q1

SCES842 – AUGUST 2012

www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

FUNCTION TABLE

(EACH GATE)

INPUTS

OUTPUT

Y

A

B

H

X

H

X

H

H

L

L

L

LOGIC DIAGRAM (POSITIVE LOGIC)

ABSOLUTE MAXIMUM RATINGS

(1)

over operating free-air temperature range (unless otherwise noted)

MIN

MAX

UNIT

VCC

Supply voltage range

–0.5

6.5

V

VI

Input voltage range(2)

–0.5

6.5

V

VO

Voltage range applied to any output in the high-impedance or power-off state(2)

–0.5

6.5

V

VO

Voltage range applied to any output in the high or low state(2) (3)

–0.5

VCC + 0.5

V

IIK

Input clamp current

VI < 0

–50

mA

IOK

Output clamp current

VO < 0

–50

mA

IO

Continuous output current

±50

mA

Continuous current through VCC or GND

±100

mA

Tstg

Storage temperature range

–65

150

°C

Human body model (HBM) AEC-Q100 classification level H2

2

kV

ESD Rating

Charged device model (CDM) AEC-Q100 classification level C3B

750

V

(1)

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2)

The input negative-voltage and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

(3)

The value of VCC is provided in the recommended operating conditions table.

THERMAL INFORMATION

SN74LVC2G32-Q1

THERMAL METRIC(1)

UNIT

DCU (8 PINS)

θJA

Junction-to-ambient thermal resistance

204.4

θJCtop

Junction-to-case (top) thermal resistance

77

θJB

Junction-to-board thermal resistance

83.2

°C/W

ψJT

Junction-to-top characterization parameter

7.1

ψJB

Junction-to-board characterization parameter

82.7

θJCbot

Junction-to-case (bottom) thermal resistance

N/A

(1)

For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

2

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