| Electronic Components Datasheet Search |
|
THS7347IPHPR Datasheet(PDF) 18 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
THS7347IPHPR Datasheet(HTML) 18 Page - Texas Instruments |
|
18 / 35 page ![]() A =No Acknowledge(SDA High) A = Acknowledge S=StartCondition P =StopCondition W=Write R=Read A A A P DATA DATA S Slave Address FromTransmitter FromReceiver W A6 A5 2 A0 A1 ACK Acknowledge (FromReceiver) ICDevice Addressand Read/WriteBit R/W D7 D6 D0 D0 ACK Stop Condition Acknowledge (Receiver) LastDataByte SDA D7 D6 D1 D1 FirstData Byte Start Condition Acknowledge (Transmitter) ACK Other DataBytes A =No Acknowledge(SDA High) A = Acknowledge S=StartCondition P =StopCondition W=Write R=Read A A A P DATA DATA S Slave Address Transmitter Receiver R A6 2 A0 ACK Acknowledge (From Receiver) ICDevice Addressand Read/WriteBit R/W D7 D0 ACK Stop Condition Acknowledge (From Transmitter) LastDataByte SDA D7 D6 D1 D0 ACK FirstData Byte Start Condition Not Acknowledge (Transmitter) Other DataBytes THS7347 SLOS531B – MAY 2007 – REVISED OCTOBER 2011 www.ti.com During a write cycle, the transmitting device must not drive the SDA signal line during the acknowledge cycle, so that the receiving device may drive the SDA signal low. After each byte transfer following the address byte, the receiving device pulls the SDA line low for one SCL clock cycle. A stop condition is initiated by the transmitting device after the last byte is transferred. Figure 9 and Figure 10 show an example of a write cycle. Note that the THS7347 does not allow multiple write transfers to occur. See the example, Writing to the THS7347, in WRITE AND READ EXAMPLES for more information. Figure 9. I2C Write Cycle Figure 10. Multiple Byte Write Transfer During a read cycle, the slave receiver acknowledges the initial address byte if it decodes the address as its address. Following this initial acknowledge by the slave, the master device becomes a receiver and acknowledges data bytes sent by the slave. When the master has received all of the requested data bytes from the slave, the not acknowledge (A) condition is initiated by the master by keeping the SDA signal high just before it asserts the stop (P) condition. This sequence terminates a read cycle, as shown in Figure 11 and Figure 12. Note that the THS7347 does not allow multiple read transfers to occur. See the example, Reading from the THS7347, in WRITE AND READ EXAMPLES for more information. Figure 11. I2C Read Cycle Figure 12. Multiple Byte Read Transfer 18 Copyright © 2007–2011, Texas Instruments Incorporated |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |