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TLV6003DBVR Datasheet(PDF) 18 Page - Texas Instruments |
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TLV6003DBVR Datasheet(HTML) 18 Page - Texas Instruments |
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18 / 26 page ![]() CBYPASS Minimize parasitic inductance by placing bypass capacitor close to VCC. RF Route trace under package for output to feedback resistor connection. VCC -IN +IN GND OUT Keep high impedance input signal away from noisy traces. VIN VOUT VCC 18 TLV6003 SLOS981 – OCTOBER 2019 www.ti.com Product Folder Links: TLV6003 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated 9 Power Supply Recommendations The TLV6003 is specified for operation from 2.5 V to 16 V (±1.25 V to ±8 V) over a –40°C to +125°C temperature range. CAUTION Supply voltages larger than 17 V can permanently damage the device. For proper operation, the power supplies must be properly decoupled. For decoupling the supply lines, place 100 nF capacitors as close as possible to the operational amplifier power supply pins. For single-supply operation, place a capacitor between VCC and GND supply leads. For dual supplies, place one capacitor between VCC and ground, and one capacitor between GND and ground. Low-bandwidth nanopower devices do not have good high-frequency (> 1 kHz) AC PSRR rejection against high- frequency switching supplies and other 1-kHz and greater noise sources. Therefore, use extra supply filtering if kilohertz or greater noise is expected on the power supply lines. 10 Layout 10.1 Layout Guidelines • Bypass the VCC pin to ground with a low ESR capacitor. • The best placement is closest to the VCC and ground pins. • Take care to minimize the loop area formed by the bypass capacitor connection between VCC and ground. • Connect the ground pin to the PCB ground plane at the pin of the device. • Place the feedback components as close as possible to the device to minimize strays. 10.2 Layout Example Figure 35. SOT-23 Layout Example (Top View) |
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