NB681- 28V, 6 A, HIGH-CURRENT SYNCHRONOUS BUCK CONVERTER WITH 2-BIT VID

NB681 Rev. 1.04

www.MonolithicPower.com

13

12/28/2017

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As the output current increases from the light-

load condition, the time period within which the

current modulator regulates becomes shorter.

The HS-FET is turned on more frequently; the

switching frequency increases accordingly. The

output current reaches the critical level when the

current modulator time is zero. The critical level

of the output current is determined with Equation

(1):

IN

OUT

OUT

OUT

SW

IN

(V

V

) V

I

2L F

V









(1)

The device enters PWM mode once the output

current exceeds the critical level. After that, the

switching frequency stays fairly constant over the

output current range.

DC Auto-Tune Loop

NB681 applies a DC auto-tune loop to balance

the DC error between VFB and VREF by adjusting

the comparator input REF to make VFB always

follow VREF. This loop is quite slow, so it improves

the load and line regulation without affecting the

transient performance. The relationship between

VFB,VREF, and REF is shown in Figure 4.

Figure 4—DC auto-tune loop operation

VCCIO/PRIMCORE/EDRAM/EOPIO/V1.0A

MODE Select

NB681 combines mode selection to support

different rails in IMVP8 including VCCIO,

PRIMCORE, EDRAM, EOPIO, and V1.0A. These

rails have different (normal) VID and different

voltages in LPM, VID slew rate, and other

features. By selecting a different resistor from

MODE to GND, NB681 can be applied in

different rails with proper features. Table 1 shows

resistor settings on MODE to enter different rails.

Table 1—MODE selection for different rails

MODE VR Rail

Resistor to GND

(1% accuracy)

M1

VCCIO

0

M2

PRIMCORE

Float or > 230 K

M3

EDRAM/V1.0A/EOPIO

100 K

M4

Others

150 K

Low-Power Mode

To minmize power loss at light-load, NB681

enters low-power mode once LP# is set to low.

NB681 is allowed to decay to the LPM target

value with the assertion of LP#. When the VR

enters LPM, it behaves in the following manner:



PG remains high to all power good logic;



VR stops switching;



The output decays into the load (discharge

circuitry is off) and decays to 0 V.

Once LP# changes from 0 V1 V, NB681 exits

LPM by ramping up Vout (with a proper delay

and slew rate) to make sure the output is ready in

240 µs, including the delay time (Tdelay). The

operation timing and slew rate of the LP# and

Vout is shown in Figure 5.

Figure 5—LPM voltage transition and timing

The LPM target value, slew rate, and PG state

for different rails are listed in Table 2.

Table 2—Intel LPM specification for each rail

PRIMCORE

VCCIO

EDRAM/

EOPIO

OTHER

LPM

target(V)

0.7

0

0

0

LPM enter

Decay

Decay

Decay

Decay

LPM exit

timer(μs)

45

240

240

240

PG during

LPM

High

High

High

High

Control Bit Definitions (LP#, VID)

The control bit definitions including LP# and VIDx

for different rails are shown in Table 3.