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ISL81601 Datasheet(PDF) 39 Page - Renesas Technology Corp

Part # ISL81601
Description  80V Bidirectional 4-Switch Synchronous Buck-Boost Controller
PDF  50 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

ISL81601 Datasheet(HTML) 39 Page - Renesas Technology Corp

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ISL81801
5. Functional Description
FN8937 Rev.1.4
Page 39 of 49
Mar 8, 2024
N-channel MOSFET is generated by a flying capacitor boot circuit. A boot capacitor connected from the BOOT pin
to the PHASE node provides power to the high-side MOSFET driver. As shown in Figure 55, the boot capacitor is
charged up to VDD by an external Schottky diode during low-side MOSFET on-time (phase node low). To limit the
peak current in the Schottky diode, an external resistor is placed between the BOOT pin and the boot capacitor.
This small series resistor also damps any oscillations caused by the resonant tank of the parasitic inductances in
the traces of the board and the FET’s input capacitance.
At start-up, the low-side MOSFET turns on first and forces PHASE to ground to charge the BOOT capacitor to 8V
if the diode voltage drop is ignored. After the low-side MOSFET turns off, the high-side MOSFET is turned on by
closing an internal switch between BOOT and UGATE. This provides the necessary gate-to-source voltage to turn
on the upper MOSFET, an action that boosts the 8V gate drive signal above VIN. The current required to drive the
upper MOSFET is drawn from the internal 8V regulator supplied from either VIN or EXTBIAS pin.
The BOOT to PHASE voltage is monitored internally. When the voltage drops to 5.95V at no switching condition,
a minimum off-time pulse is issued to turn off the upper MOSFET and turn on the low-side MOSFET to refresh the
bootstrap capacitor and maintain the upper driver bias voltage.
To optimize EMI performance or reduce phase node ringing, a small resistor is placed between the BOOT pin to
the positive terminal of the bootstrap capacitor.
5.14 Power-Good Indicator
The power-good pin can monitor the status of the output voltage. PGOOD is true (open drain) 1.1ms after the
FB_OUT pin is within ±10% of the reference voltage.
There is no extra delay when the PGOOD pin is pulled LOW.
Figure 55. Upper Gate Driver Circuit
BOOT
UGATE
PHASE
VDD
VIN
ISL81801
CB
RBOOT
External
Schottky



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