March 26, 2021

CONFIDENTIAL Rev. 3.6

ES9018K2M Datasheet

7

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA. Tel (408) 643-

8800 • www.esstech.com

System Clock (XI / MCLK)

A system clock is required for proper operation of the digital filters and modulation circuitry. See p.30, Note 2 for the

maximum MCLK frequencies supported. The minimum system clock frequency must also satisfy:

Data Type

Minimum MCLK Frequency

Note

DSD Data

MCLK > 3 x FSR , FSR = 2.8224MHz (x 1, 2 or 4)

The maximum FSR

frequency is further

limited by the maximum

MCLK frequencies

supported as shown p.30,

Note 2.

Serial Normal Mode

MCLK > 192 x FSR, FSR

 384kHz

or

MCLK = 128 x FSR (synchronous MCLK) with FSR

 384kHz

Serial OSF Bypass Mode

MCLK > 24 x FSR, FSR

 1.536MHz

SPDIF Data

MCLK > 386 x FSR, FSR

 200kHz

Data Clock

DATA_CLOCK must be (2 x i2s_length) x FSR for SERIAL, and FSR for DSD modes. For SPDIF mode, this pin is used for

SPDIF input. This pin should be pulled low if not used.

Built-in Digital Filters

Three digital filters (fast roll-off, slow roll-off filters and minimum phase filter) are included for PCM data. See 'PCM Filter

Characteristics' for more information.

Standby Mode

For lowest power consumption the followings should be performed to enter stand-by mode:

•

Set the soft_start bit in register 14 to 1'b0 to ramp the DAC outputs (DACL, DACLB, DACR, DACRB) to ground.

•

RESETB pin should be brought to low digital level to:

o

Shut off the DACs, Oscillator and internal regulator.

o

Force digital I/O pins (DATA_CLK, DATA1, GPIO1, GPIO2, SDA ) into tri-state mode

o

Reset all registers to default states

•

If XI/MCLK is supplied externally, it should be stopped at logic low level

•

If DVDD is supplied by an external regulator, it should be shut down during standby.

To resume from standby mode, bring RESETB to high digital level and reinitialize all registers.

DVDD Supply

The ES9018K2M is equipped with a regulated DVDD supply powered from DVCC. The internal DVDD regulator must be

decoupled to DGND with a capacitor that maintains a minimum value of 1

F at 1.2V over the target operating temperature

range. The recommended capacitor for decoupling DVDD is a 2.2

F ±20%, X5R 6.3V 0402, e.g. TDK part number

C1005X5R0J225M050BC or similar.

•

The internal DVDD should be used except under the following conditions:

PCM (SPDIF, I2S with OSF Bypass off or on): MCLK > 50MHz or FSR > 192kHz

DSD: MCLK > 50MHz or FSR > 11.2MHz

•

Internal DVDD may be used up to the maximum supported MCLK frequencies specified on p.29, Note 2. An External

DVDD (+1.3V) supply must be used above those frequencies. The external supply voltage must be greater than the

internal supply of +1.2V so the internal supply is disabled.