ADC08B200

SNAS388F – MARCH 2007 – REVISED APRIL 2013

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THE REN PIN

A high level at this Read Enable input causes data to be read from the capture buffer. One byte is read with the

rise of each RCLK input. This signal should go high synchronous with the RCLK input and should not be high

while the WEN input is high. If this input is high while the WEN input is high, the WEN input has priority and the

REN input is ignored, regardless of which of these two inputs is high first. It is not possible to read from the buffer

while a write to the buffer is in progress.

THE ASW PIN

This Auto-Stop Write input has a dual function. With writing to the buffer enabled and this ASW high, this pin acts

as the ASW (Auto-Stop Write) input, which causes writing to the buffer to halt once the buffer is full (FF high).

This prevents write "wrap around" and the over-writing of older data. When writing to the buffer is disabled, this

pin is ignored. When the device is in Test Mode, this pin acts as the Output Edge Select input and functions as

described for the OEDGE/TEN input.

THE BSIZE PINS

The two Buffer Size input pins (BSIZE0 and BSIZE1) are used to select the required buffer size for the

application or to bypass the buffer altogether. Refer to USING THE DATA BUFFER for use of these pins

PLL CONTROL: THE MULT PINS

The two MULT input pins (MULT0 and MULT1) are used to select the CLK Multiplier for the internal PLL, or to

bypass the PLL. Refer to CLOCK OPTIONS for more information.

DIGITAL OUTPUT PINS

The ADC08B200 has 12 digital output pins: 8 Digital Data Output pins, DRDY, WENSYNC, EF and FF

Digital Data Outputs

This 8-bit bus is LVTTL/LVCMOS compatible, with a Straight Binary output format. Data is clocked out on this

bus in one of two ways. When the internal buffer is bypassed, data is clocked out at the sample clock rate. When

the internal buffer is used, data is clocked out at the RCLK rate. In either case, data is clocked out on the rising

edge of the appropriate clock. Refer to CLOCK OPTIONS for information on sample rate determination.

When the Capture Buffer is bypassed, data is read directly from the converter at the sample clock rate.

When the capture buffer is used, data is read from the capture buffer and presented at these pins when the REN

input is high. If OEDGE/TEN is high, the digital data output and DRDY are held low when no valid data is being

sent out. If OEDGE/TEN is low, the digital data and DRDY are held high when no valid data is being sent out.

These pins source data at the converter sample rate when the buffer is disabled.

Whether the buffer is enabled or not, the output data is provided synchronous with DRDY. That is, the data

transition occurs with the edge of DRDY defined by OEDGE/TEN such that the data transitions on the rise of

DRDY if OEDGE/TEN is high or on the fall of DRDY if OEDGE/TEN is low.

The data output drivers are capable of sourcing and sinking a relatively high current to enable rapid charging and

discharging of the output capacitance, thereby allowing fast output rise and fall times. The data outputs should

be as lightly loaded as possible to minimize on-chip noise and the resulting loss of SNR performance. Note the

specified load capacitance at the heading of the Electrical Characteristics Tables.

The DRDY Pin

This output is intended for use to latch output data into a receiving device and transitions with the transition of

the digital data outputs. The synchronizing edge of the DRDY signal can be selected with the OEDGE input.

When the buffer is not used, DRDY is active as long as the ADC is functioning. When the buffer is enabled,

DRDY is active only while data is being sent out. When no valid data is being sent out, the DRDY output sense is

the opposite of the OEDGE input. When OE is low and the device is NOT in the Test Pattern Mode (OEDGE

floating or at VA / 2), the DRDY output is in the high impedance state, as are the data outputs. However, in Test

Pattern Mode the OE input is ignored and all output drivers (data and DRDY) are in the active state. When the

buffer is used, DRDY is held low at all times except during the buffer read phase, where it switches in

synchronism with the data output pins.

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