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PIC32MX330F064L Datasheet(PDF) 94 Page - Microchip Technology |
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PIC32MX330F064L Datasheet(HTML) 94 Page - Microchip Technology |
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94 / 360 page ![]() 10.1 Control Registers TABLE 10-1: DMA GLOBAL REGISTER MAP Bits 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 3000 DMACON 31:16 — — — — — — — — — — — — — — — — 0000 15:0 ON — — SUSPEND DMABUSY — — — — — — — — — — — 0000 3010 DMASTAT 31:16 — — — — — — — — — — — — — — — — 0000 15:0 — — — — — — — — — — — — RDWR DMACH<2:0> 0000 3020 DMAADDR 31:16 DMAADDR<31:0> 0000 15:0 0000 Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for more information. TABLE 10-2: DMA CRC REGISTER MAP Bits 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 3030 DCRCCON 31:16 — — BYTO<1:0> WBO — — BITO — — — — — — — — 0000 15:0 — — — PLEN<4:0> CRCEN CRCAPP CRCTYP — — CRCCH<2:0> 0000 3040 DCRCDATA 31:16 DCRCDATA<31:0> 0000 15:0 0000 3050 DCRCXOR 31:16 DCRCXOR<31:0> 0000 15:0 0000 Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 “CLR, SET, and INV Registers” for more information. |
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