DT

CK

t(BUF)

t(D-SU)

t(D-HD)

Start

t(LOW)

t(S-HD)

t(CK-F)

t(CK-R)

t(HI)

Repeated Start

t(RS-SU)

t(RS-HD)

t(DT-F)

t(DT-R)

t(P-SU)

Stop

T0050-02

PCM2704

,, PCM2705

PCM2706, PCM2707

SLES081F – JUNE 2003 – REVISED JANUARY 2009....................................................................................................................................................... www.ti.com

SYMBOL

PARAMETER

MIN

MAX

UNIT

f(CK)

CK clock frequency

100

kHz

t(BUF)

Bus free time between a STOP and a START condition

4.7

µs

t(LOW)

Low period of the CK clock

4.7

µs

t(HI)

High period of the CK clock

4

µs

t(RS-SU)

Setup time for START/repeated START condition

4.7

µs

t(S-HD)

Hold time for START/repeated START condition

4

µs

t(RS-HD)

t(D-SU)

Data setup time

250

ns

t(D-HD)

Data hold time

0

900

ns

t(CK-R)

Rise time of CK signal

20 + 0.1 CB 1000

ns

t(CK-F)

Fall time of CK signal

20 + 0.1 CB 1000

ns

t(DT-R)

Rise time of DT signal

20 + 0.1 CB 1000

ns

t(DT-F)

Fall time of DT signal

20 + 0.1 CB 1000

ns

t(P-SU)

Setup time for STOP condition

4

µs

CB

Capacitive load for DT and CK lines

400

pF

VNH

Noise margin at HIGH level for each connected device (including hysteresis)

0.2 VDD

V

Figure 26. External ROM Read Interface Timing Requirements

22

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