IN

Clipping

Clipping

V

V

2 V

u

ModulatorOutput

AnalogInput

+FS(AnalogInput)

-FS(AnalogInput)

21

AMC1336-Q1

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SBASA51 – MAY 2020

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Feature Description (continued)

7.3.4 Clock Input

The AMC1336-Q1 system clock is provided externally at the CLKIN pin. The clock signal must be applied

continuously for proper device operation.

To support the bipolar input voltage range with a unipolar high-side supply AVDD, the AMC1336-Q1 includes a

charge pump. This charge pump stops operating if the clock signal is below the specified frequency range or if

the signal is paused or missing. In that case, the input bias current increases beyond the specified range and

significantly reduces the input resistance of the device. When the clock signal is paused or missing, the

modulator stops the analog signal conversion and the digital output signal remains frozen in the last logic state.

When the clock signal is applied again after a pause, the internal analog circuitry biasing must settle for proper

device performance. In this case, consider the tASTART specification in the Switching Characteristics table.

7.3.5 Digital Output

A differential input signal of 0 V ideally produces a stream of ones and zeros that are high 50% of the time. A

differential input of 1 V produces a stream of ones and zeros that are high 90% of the time. With 16 bits of

resolution, that percentage ideally corresponds to code 58982 (an unsigned code). A differential input of –1 V

produces a stream of ones and zeros that are high 10% of the time and ideally results in code 6553 with 16-bit

resolution. These input voltages are also the specified linear range of the AMC1336-Q1 with performance as

specified in this document. If the input voltage value exceeds this range, the output of the modulator shows

nonlinear behavior when the quantization noise increases. The output of the modulator clips with a stream of only

zeros with an input less than or equal to –1.25 V or with a stream of only ones with an input greater than or equal

to 1.25 V. In this case, however, the AMC1336-Q1 generates a single 1 (if the input is at negative full-scale) or 0

every 128 clock cycles to indicate proper device function (see the AVDD Diagnostics and Fail-Safe Output

section for more details). Figure 45 shows the input voltage versus the output modulator signal.

Figure 45. Analog Input versus the AMC1336-Q1 Modulator Output

Equation 1 calculates the density of ones in the output bitstream for any input voltage value (with the exception

of a full-scale input signal, as described in the Output Behavior in Case of a Full-Scale Input section):

(1)

The modulator bitstream on the DOUT pin changes with the rising edge of the clock signal applied on the CLKIN

pin. Use the rising edge of the clock to latch the modulator bitstream at the input of the digital filter device.