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ESDS312 Datasheet(PDF) 5 Page - Texas Instruments

Part # ESDS312
Description  ESDS31x Data-Line Surge and ESD Protection Diode Array
PDF  24 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

ESDS312 Datasheet(HTML) 5 Page - Texas Instruments

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5.5 Thermal Information (continued)
THERMAL METRIC (1)
ESDS311
ESDS312
ESDS314
UNIT
DYF (SOD323)
DBV (SOT-23)
DBV (SOT-23)
2 PINS
5 PINS
5 PINS
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
5.6 Electrical Characteristics
At TA = 25°C unless otherwise noted
PARAMETER
TEST CONDITIONS
Device
MIN
TYP
MAX
UNIT
VRWM
Reverse stand-off voltage
IIO < 500nA, across operating
temperature range
3.6
V
ILEAKAGE
Leakage current at 3.6V
VIO = 3.6V, Any IO pin to GND
5
50
nA
VBRF
Breakdown voltage, IO to GND (1) IIO = 1mA
4.5
7.5
V
VFWD
Forward Voltage, GND to IO
IIO = 1mA
0.8
V
VHOLD
Holding Voltage, IO to GND (2)
IIO = 1mA
5
V
VCLAMP
Surge Clamping voltage, tp =
8/20µs
IPP = 1A, Any IO pin to GND
ESDS312/314
5
V
VCLAMP
IPP = 12A, Any IO pin to GND
ESDS311
6.3
V
ESDS312/314
5.6
VCLAMP
IPP = 25A, Any IO pin to GND
ESDS311
7.7
V
ESDS312/314
6.5
VCLAMP
IPP = 1A, GND to any IO pin
ESDS312/314
1
V
VCLAMP
IPP = 12A, GND to any IO pin
ESDS311
3
V
ESDS312/314
2.1
VCLAMP
IPP = 25A, GND to any IO pin
ESDS311
4.9
V
ESDS312/314
3.6
VCLAMP
TLP Clamping Voltage, tp =
100ns
IPP = 16A, Any IO pin to GND
ESDS311
6.5
V
ESDS312/314
5.5
VCLAMP
IPP = 16A, GND to any IO pin
ESDS311
3.4
V
ESDS312/314
2.2
CLINE
Line capacitance, Any IO to GND VIO = 0V, Vp-p = 30mV, f = 1MHz
4.5
5.5
pF
ΔCLINE
Variation of line capacitance
CLINE1 - CLINE2, VIO = 0V, Vp-p =
30mV, f = 1MHz
ESDS312/314
0.05
0.1
pF
CCROSS
Line-to-line capacitance
VIO = 0V, Vrms = 30mV, f = 1MHz ESDS312/314
2.25
2.75
pF
(1)
VBRF and VBRR are defined as the voltage obtained at 1mA when sweeping the voltage up, before the device latches into the snapback
state
(2)
VHOLD is defined as the voltage when 1mA is applied, after the device has successfully latched into the snapback state.
www.ti.com
ESDS311, ESDS312, ESDS314
SLVSEG9C – MAY 2018 – REVISED FEBRUARY 2024
Copyright © 2024 Texas Instruments Incorporated
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Product Folder Links: ESDS311 ESDS312 ESDS314



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