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STM32WB10CCU5 Datasheet(PDF) 81 Page - STMicroelectronics

Part # STM32WB10CCU5
Description  Multiprotocol wireless 32-bit MCU Arm®-based Cortex®-M4 with FPU, Bluetooth® 5.2 radio solution
PDF  110 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32WB10CCU5 Datasheet(HTML) 81 Page - STMicroelectronics

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DS13259 Rev 2
81/110
STM32WB10CC
Electrical characteristics
102
Low-speed internal (LSI) RC oscillator
6.3.11
PLL characteristics
The parameters given in Table 53 are derived from tests performed under temperature and
VDD supply voltage conditions summarized in Table 20: General operating conditions.
Table 51. LSI1 oscillator characteristics(1)
Symbol
Parameter
Conditions
Min
Typ Max Unit
fLSI
LSI1 frequency
VDD = 3.0 V, TA = 30 °C
31.04
-
32.96
kHz
VDD = 2.0 to 3.6 V, TA = –10 to 85 °C
29.5
-
34
tSU(LSI1)(2) LSI1 oscillator start-up time
-
-
80
130
μs
tSTAB(LSI1)(2) LSI1 oscillator stabilization time 5% of final frequency
-
125
180
IDD(LSI1)(2)
LSI1 oscillator power
consumption
-
-
110
180
nA
1. Evaluated by characterization, not tested in production.
2. Specified by design, not tested in production.
Table 52. LSI2 oscillator characteristics(1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fLSI2
Frequency(2)
VDD = 2.0 to 3.6 V, TA = –10 to 85 °C
22
32
48
kHz
tSU(LSI2)(3)
Start-up time
-
1
-
3.5
ms
IDD(LSI2)(3)
Power consumption
-
-
1
2
μA
∆TEMP(LSI2) Stability over temperature
-
-200
-
200
ppm / °C
1. Evaluated by characterization, not tested in production.
2. LSI2 cannot be trimmed.
3. Specified by design, not tested in production, LSI2TRIM[3:0] field of register RCC_CSR = 0xC.
Table 53. PLL characteristics(1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fPLL_IN
PLL input clock(2)
-2.66
-
16
MHz
PLL input clock duty cycle
-
45
-
55
%
fPLL_P_OUT PLL multiplier output clock P
-
2
-
64
MHz
fPLL_Q_OUT PLL multiplier output clock Q
-
8
-
64
fPLL_R_OUT PLL multiplier output clock R
-
8
-
64
fVCO_OUT PLL VCO output
-
96
-
344
tLOCK
PLL lock time
-
-
15
40
μs
Jitter
RMS cycle-to-cycle jitter
System clock 64 MHz
-40
-
ps
RMS period jitter
-
30
-



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