STM32WB10CCU5 datasheet(109/110 Pages) STMICROELECTRONICS

109 / 110 page

DS13259 Rev 2

109/110

STM32WB10CC

Revision history

109

Revision history

Table 81. Document revision history

Date

Revision

Changes

17-Feb-2021

Initial release.

09-Jun-2021

Updated Features, Section 1: Introduction, Section 2: Description,

Section 3.6: RF subsystem, Section 3.6.2: BLE general description,

Section 3.7.4: Low-power modes, Section 3.10: Clocks and startup,

Section 6.1.6: Power supply scheme and Section 6.3.9: External clock

source characteristics.

Updated Table 1: STM32WB10CC device features and peripheral counts,

Table 5: Functionalities depending on system operating mode, Table 6:

STM32WB10CC modes overview, Table 19: Main performance at VDD =

3.3 V and its footnote 2, Table 20: General operating conditions,

Table 24: RF BLE power consumption for VDD = 3.3 V, Table 34: Current

consumption in Stop 1 mode, Table 35: Current consumption in Stop 0

mode, Table 36: Current consumption in Standby mode, Table 41: Low-

power mode wakeup timings, Table 42: Regulator modes transition times,

Table 45: HSE clock source requirements, Table 46: HSE oscillator

characteristics, Table 52: LSI2 oscillator characteristics and its footnote 3,

Table 61: I/O static characteristics and Table 68: ADC accuracy.

Added Table 43: Wakeup time using USART.

Updated Figure 6: Clock tree, Figure 19: ADC accuracy characteristics,

Figure 20: Typical connection diagram when using the ADC with FT/TT

pins featuring analog switch function and its footnotes.

Minor text edits across the whole document.

STM32WB10CCU5 Datasheet(PDF) 109 Page - STMicroelectronics