LMX2486 datasheet(21/48 Pages) TI2

Part #	LMX2486

Description	LMX2486 1-GHz to 4.5-GHz High-Performance Delta-Sigma Low-Power Dual PLLatinum™ Frequency Synthesizers With 3-GHz Integer PLL

PDF	48 Pages

Scroll/Zoom	100%

Manufacturer	TI2 [Texas Instruments]

Direct Link	https://www.ti.com

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21 / 48 page

YES

Phase Error < H

LD = LOW

(Not Locked)

Phase Error < H

LD = HIGH

(Locked)

Phase Error < H

Phase Error > G

YES

START

YES

Phase Error < H

LMX2486

www.ti.com

SNAS324B – JANUARY 2006 – REVISED JANUARY 2016

Figure 22. Digital Lock Detect Flowchart

8.3.7 Cycle Slip Reduction and Fastlock

The LMX2486 offers both cycle slip reduction (CSR) and Fastlock with timeout counter support. This means that

it requires no additional programming overhead to use them. It is generally recommended that the charge pump

current in the steady-state be 8X or less to use cycle slip reduction, and 4X or less in steady-state to use

Fastlock. The next step is to decide between using Fastlock or CSR. This determination can be made based on

the ratio of the comparison frequency (fCOMP) to loop bandwidth (BW).

Table 7. Fastlock/Cycle Slip Reduction Usage

COMPARISON FREQUENCY

CYCLE SLIP REDUCTION

FASTLOCK

(fCOMP)

(CSR)

fCOMP ≤ 1.25 MHz

Noticeable better than CSR

Likely to provide a benefit, provided that

1.25 MHz < fCOMP ≤ 2 MHz

Marginally better than CSR

fCOMP > 100 X BW

fCOMP > 2 MHz

Same or worse than CSR

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LMX2486 Datasheet(PDF) 21 Page - Texas Instruments