tDELAY =

VTH(SET) X CSET

ISET

LP3996

SNVS360D – NOVEMBER 2006 – REVISED OCTOBER 2013

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Enable Control

The LP3996 features active high enable pins for each regulator, EN1 and EN2, which turns the corresponding

LDO off when pulled low. The device outputs are enabled when the enable lines are set to high. When not

enabled the regulator output is off and the device typically consumes 2nA.

If the application does not require the Enable switching feature, one or both enable pins should be tied to VIN to

keep the regulator output permanently on.

To ensure proper operation, the signal source used to drive the enable inputs must be able to swing above and

below the specified turn-on / off voltage thresholds listed in the Electrical Characteristics section under VIL and

VIH.

Power-On-Reset

The POR pin is an open-drain output which will be set to Low whenever the output of LDO2 falls out of regulation

to approximately 90% of its nominal value. An external pull-up resistor, connected to VOUT or VIN, is required on

this pin. During start-up, or whenever a fault condition is removed, the POR flag will return to the High state after

the output reaches approximately 96% of its nominal value. By connecting a capacitor from the SET pin to GND,

a delay to the rising condition of the POR flag may be introduced. The delayed signal may then be used as a

Power-on -Reset for a microprocessor within the user's application.

The duration of the delay is determined by the time to charge the delay capacitor to a threshold voltage of 1.25V

at 1.2 µA from the SET pin as in the formula below.

(1)

A 0.1 µF capacitor will introduce a delay of approximately 100 ms.

Bypass Capacitor

The internal voltage reference circuit of the LP3996 is connected to the CBYP pin via a high value internal resistor.

An external capacitor, connected to this pin, forms a low-pass filter which reduces the noise level on both outputs

of the device. There is also some improvement in PSSR and line transient performance. Internal circuitry ensures

rapid charging of the CBYP capacitor during start-up. A 10 nF, high quality ceramic capacitor with either NPO or

COG dielectric is recommended due to their low leakage characteristics and low noise performance.

Safe Area of Operation

Due consideration should be given to operating conditions to avoid excessive thermal dissipation of the LP3996

or triggering its thermal shutdown circuit. When both outputs are enabled, the total power dissipation will be

PD(LDO1) + PD(LDO2) Where PD = (VIN - VOUT) x IOUT for each LDO.

In general, device options which have a large difference in output voltage will dissipate more power when both

outputs are enabled, due to the input voltage required for the higher output voltage LDO. In such cases,

especially at elevated ambient temperature, it may not be possible to operate both outputs at maximum current

at the same time.

14

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