STA382BWSTR datasheet(68/172 Pages) STMICROELECTRONICS

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STA382BWS

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Doc ID 022784 Rev 1

6.19

Volume control registers (addr 0x17 - 0x1B)

6.19.1

Mute/line output configuration register (addr 0x17)

Line output is only active when OCFG = 00. In this case LOC determines the line output

configuration. The source of the line output is always the channel 1 and 2 inputs.

Table 55.

Mute configuration

LOC1

LOC0

Reserved

C3M

C2M

C1M

MMUTE

Table 54.

Line output configuration

LOC[1:0]

Line output configuration

Line output fixed - no volume, no EQ

Line output variable - CH3 volume effects line output, no EQ

Line output variable with EQ - CH3 volume effects line output

Reserved

Bit

R/W

RST

Name

Description

3R/W

C3M

Channel 3 mute

0 - No mute condition. It is possible to set the channel

volume

1 - Channel 3 in hardware mute

2R/W

C2M

Channel 2 mute

0 - No mute condition. It is possible to set the channel

volume

1 - Channel 2 in hardware mute

1R/W

C1M

Channel 1 mute

0 - No mute condition. It is possible to set the channel

volume

1 - Channel 1 in hardware mute

R/W

MMUTE

Master mute

0 - Normal operation

1 - All channels are in mute condition

Obsolete

Product(s)

- Obsolete

Product(s)

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