MB97R8110-WF datasheet(32/63 Pages) RAMXEED

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DS411-00007-3v1-E

MB97R8110

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7 Extended Application

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7.1 SPI master

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7.1.1 SPI master setting

SPI master mode is enabled by Write command to WordPtr=9E02h(WordAdr=F02h) of USER bank. It is

necessary to enable setting every power on cycle. The setting value can be read by Read command, but the value

will be reset to “0000h” under the following condition.

•

Power off after setting

•

Internal reset by low power detection

In these cases, it is necessary to set the value again by Write command in order to enable SPI master mode.

The data format of SPI master setting register is shown in Table7.1.1.

Table 7.1.1 –Data format of SPI Master setting

MSB

LSB

15 14 13 12 11 10

En Mux

Dio

Rst

Ctl

Re-

served

SetupStart

Reserved

DivClk

En: Master operation Enable/Disable setting

bit

Initial value

Setting

Setting description

SPI master operation Disable

SPI master operation Enable

MuxDio: Multiplex setting for DI and DO (refer to Chapter 7.1.2)

bit

Initial value

Setting

Setting description

Separate for DI and DO

Multiplex for DI and DO

RstCtl: XRST control

bit

Initial value

Setting

Setting description

XRST is "L" level output

XRST is "H" level output

Reserved

bit

Initial value

Setting

Setting description

Set to 0

SetupStart[3:0]: setting number of clock cycles between command receiving and XCS dropping

bit

Initial value

Setting

Setting description

11:8

Setup=N*8 clock (N＝1 to 15)

Clock Frequency above is SCK output frequency described in DivClk.

Reserved

bit

Initial value Setting

Setting description

7:4

Set to 0

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