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STM32WL33CBV7 Datasheet(PDF) 11 Page - STMicroelectronics

Part # STM32WL33CBV7
Description  Multiprotocol LPWAN 32-bit MCU Arm® Cortex®-M0 2(G)FSK, 4(G)FSK, ASK, D-BPSK, up to 256KB flash, 32KB SRAM
PDF  91 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32WL33CBV7 Datasheet(HTML) 11 Page - STMicroelectronics

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Figure 4. Wake up radio block diagram
Interruptible Power
domain
Switchable
Registers
Always-on Power domain
Digital
Controller
interrupt
WakeUp radio IP
AHB2APB
IRQ
Wake-up event
Sleep allowance
AFE Interface
Retained
Registers
APB
Management
AFE Configuration
The Receiver uses the Manchester OOK modulation only (G.E.Thomas encoding).
The default data rate is 1 kbit/s for the raw data which gives 2 kbit/s after Manchester encoding.
The frame format is a specific frame as described below, with few configurable bit fields in order to expand the
use of the WakeUp Radio IP.
The specific frame is composed of:
•
a bit sync of 40 bits defined at ‘0’
•
a frame sync of 8 bits corresponding to the pattern 0x99
•
a payload of 56 bits
•
a CRC defined on 16 bits, and calculated on the payload only
Figure 5. LPAWUR frame format
bit sync
Frame
Sync
Payload
CRC
40 bits
0x0000000000
8 bits
0x99
56 bits
16 bits
Init : 0x0000
Polynom: 0x8005
(x16 + x15 + x2 + 1)
CRC calculation
Manchester encoding
The analog section of the receiver is equipped with an automatic gain control system (AGC) which senses the
input signal level and acts to avoid saturation.
STM32WL33xx
Functional overview
DS14221 - Rev 5
page 11/91



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