STM32WL33C8V datasheet(15/91 Pages) STMICROELECTRONICS

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•

the system clock and the bus clock are running

•

the CPU core and the radio can be used

•

the power consumption may be reduced by gating the clock of the unused peripherals

3.6.2

Deepstop mode

Deepstop is the only low power mode of the STM32WL33xx allowing the restart from a saved context

environment and the application at wake-up to go on running.

The conditions to enter Deepstop mode are:

•

The radio (MR_SUBG) is sleeping (no radio activity)

•

The CPU is sleeping (WFI with SLEEPDEEP bit activated)

•

No unmasked wake-up sources are active (including those from a previous wakeup sequence for which the

software did not clear the associated flag after wakeup) the PWRC_CR1.LPMS bit is equal to 0.

•

The system is clocked on RC64MPLL (HSI or PLL locked mode)

•

Reset PWRC_CR5.GPIORET bit when PWRC_DBGR.DEEPSTOP2 bit is set, otherwise set

PWRC_CR5.GPIORET bit

•

If SMPS clock variable rate multiplier is enabled RCC_KRMR.KRMEN=1, in order to guarantee a good

SMPS startup at next wakeup, its mandatory to put RCC_CFGR.SMPSDIV=0.

In Deepstop mode:

•

The system and the bus clocks are stopped as the RC64MPLL block is OFF

•

the VDD12i power domain is switched off

•

the VDDI2o power domain is ON and supplied by the LPREG which regulated voltage is:

–

1.2 V if the LCD is enabled (LCD_CR.LCDEN=1)

–

1.2 V if the Comparator scaler is enabled (COMP.SCALEN=1)

–

1.2 V if the bit PWRC_CR2.LPREG_FORCE_VH=1

–

1.0 V in all the other cases

The current regulation status of the LPREG is reported by the PWRC_CR2.LPREG_VH_STATUS bit:

•

the RAM0 bank is kept in retention

•

the other RAM banks are in retention or not, depending on software choice in PWRC_CR2 register

•

the slow clock can be running or stopped, depending on the software configuration present before

Deepstop entry:

–

ON or OFF

–

LSE or LSI source

•

The Comparator, LCD, RTC, IWDOG, LC Sensor Controller, DAC and LPUART stay active (if enabled and

one slow clock source is ON).

•

The MR_SUBG wakeup block including its timer stay active (if enabled and one slow clock source is ON).

•

The LPAWUR RFIP wakeup block including its timer stay active (if enabled and one slow clock source is

ON).

•

The configurations of all the I/Os are latched before entering Deepstop mode:

–

AF configuration is latched only for the I/Os on which is mapped at least one pin of a peripheral that

can be active in Deepstop mode (Comparator, LCD, RTC, IWDOG, LC Sensor Controller, DAC and

LPUART)

–

I/Os analog switches configuration is retained for the I/Os on which is mapped at least one analog pin

of a peripheral that can be active in Deepstop mode (comparator)

–

all the I/Os able to be in output driving either a static low or high level, some of them also the slow

clock information LCO or the RTC_OUT.

A version of the Deepstop mode called DEEPSTOP2 has been implemented to emulate the Deepstop mode

without losing the debugger connection and breakpoints nor watchpoints.

•

This variant can be selected by setting the PWRC_DBGR.DEEPSTOP2 bit.

•

In this case, the Deepstop mode sequence (entry and exit) is done without shutting down the VDD12i

power domain.

Possible wake-up sources are:

STM32WL33xx

Functional overview

DS14221 - Rev 5

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