DAC80504 datasheet(5/50 Pages) TI2

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REF

OUT0

LDAC

OUT1

REFDIV

OUT2

RSTSEL

Not to scale

Thermal Pad

DAC80504, DAC70504, DAC60504

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SBAS871C – AUGUST 2017 – REVISED JANUARY 2019

Product Folder Links: DAC80504 DAC70504 DAC60504

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6 Pin Configuration and Functions

RTE Package

16-Pin WQFN

Top View

Pin Functions

TYPE

DESCRIPTION

NAME

NO.

REF

I/O

When using internal reference, this is the reference output voltage pin (default). When using an

external reference, this is the reference input pin to the device.

OUT0

Analog output voltage from DAC 0.

OUT1

Analog output voltage from DAC 1.

OUT2

Analog output voltage from DAC 2.

OUT3

Analog output voltage from DAC 3.

GND

Ground reference point for all circuitry on the device.

VDD

PWR

Analog supply voltage (2.7 V to 5.5 V).

GAIN

Sets the gain configuration after a power-up or reset event. When tied to GND, the initial buffer

amplifier gain for all four channels is set to 1. When tied to VIO the initial buffer amplifier gain is 2.

Changing the state of this pin after power-up does not affect the device operation.

RSTSEL

Reset select pin. When tied to GND all four DACs reset to zero scale. When connected to VIO all four

DACs reset to midscale.

REFDIV

Sets the reference divider configuration after a power-up or reset event. When tied to GND, the

reference voltage is not divided down. When tied to VIO the reference voltage is divided by 2. Changing

the state of this pin after power-up does not affect the device operation.

LDAC

A high-to-low transition on the LDAC pin causes the DAC outputs of those channels configured in

synchronous mode to update simultaneously. The pin can be tied permanently to GND.

Active low serial data enable. This input is the frame synchronization signal for the serial data. When

the signal goes low, it enables the serial interface input shift register.

SCLK

Serial interface clock.

SDI

Serial interface data input. Data are clocked into the input shift register on each falling edge of the

SCLK pin.

SDO/ALARM

Serial interface data output (default). The SDO pin is in high impedance when CS pin is high. Data are

clocked out of the input shift register on either rising or falling edges of the SCLK pin as specified by

the FSDO bit. Alternatively the pin can be configured as an ALARM open-drain output to indicate a

CRC or reference alarm event. If configured as ALARM a 10 kΩ, pull-up resistor to VIO is required.

VIO

PWR

IO supply voltage (1.7 V to 5.5 V). This pin sets the I/O operating voltage for the serial interface.

Thermal Pad

–

The thermal pad is located on the bottom-side of the QFN package. The thermal pad should be

connected to any internal PCB ground plane using multiple vias for good thermal performance.

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