DAC8728SPAG datasheet(40/59 Pages) TI2

40 / 59 page

DAC8728

SBAS466A – JUNE 2009 – REVISED NOVEMBER 2009

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UPDATING THE DAC OUTPUTS

Depending on the status of both CS and LDAC, and after data have been transferred into the DAC Data

registers, the DAC outputs can be updated either in asynchronous mode or synchronous mode. This update

mode is established at power-on. If asynchronous mode is desired, the LDAC pin must be permanently tied low

before power is applied to the device. If synchronous mode is desired, LDAC must be logic high before and

during power-on.

The DAC8728 updates a DAC latch only if it has been accessed since the last time LDAC was brought low or if

the LD bit is set to '1', thereby eliminating any unnecessary glitch. Any DAC channels that were not accessed are

not loaded again. When the DAC latch is updated, the corresponding output changes to the new level

immediately.

Asynchronous Mode

In this mode, the LDAC pin is set low at power-up. This action places the DAC8728 into Asynchronous mode,

and the LD bit and LDAC signal are ignored. When the correction engine is off (SCE bit = '0'), the DAC Data

Registers and DAC latches are updated immediately when CS goes high. When the correction engine is on (SCE

bit = '1'), each DAC latch is updated individually when the correction engine updates the corresponding DAC

Data Register.

Synchronous Mode

To activate this mode, take LDAC low or set the LD bit to '1' after CS goes high. If LDAC goes low or if the LD bit

is set to '1' when SCE = '0', all DAC latches are updated simultaneously. If LDAC goes low or if the LD bit is set

to '1' when SCE = '1' and the BUSY pin is high (GBF bit = '0'), all DAC latches are updated simultaneously. If

LDAC goes low or the LD bit is set to '1' when SCE = '1' and the BUSY pin is low (GBF bit = '1'), the DAC

latches are not updated immediately because the correction engine is still running. Instead, all DAC latches are

updated simultaneously when the GBF bit is cleared to '0'. At that time, the correction engine is finished.

In this mode, when LDAC stays high, the DAC latch is not updated; therefore, the DAC output does not change.

The DAC latch is updated by taking LDAC low (or by setting the LD bit in the Configuration Register to '1') any

time after the delay of t15 from the rising edge of CS (when the correction engine is disabled), or after the delay

of t18 from the rising edge of BUSY (when the correction engine is enabled). If the timing requirements of t15 or

t18 is not satisfied, invalid data are loaded. Refer to the Timing Diagrams and the Configuration Register

(Table 11) for details.

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DAC8728SPAG Datasheet(PDF) 40 Page - Texas Instruments