L9826 datasheet(9/19 Pages) STMICROELECTRONICS

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L9826

Electrical specifications

Doc ID 7214 Rev 10

9/19

Vclp

Output clamp voltage

1 mA

 I

clp  Ioutp; Itest = 10 mA

with correlation

RDSon

On resistance OUT 1 ... 8

IOUT = 250 mA; Tj = +150 °C

3.0



COUT

Output capacitance

VOUT = 16 V; f = 1 MHz

guaranteed by design

300

Outputs short circuit protection

ISBC

Overcurrent shutoff threshold

OUT3 ... OUT8

0.45

1.1

ILIM

Short circuit current limitation

OUT1; OUT2

0.5

1.1

tSCB

Delay shutdown

0.2

3,0

s

Diagnostics

VDG

Diagnostic threshold voltage

0.32

·VCC

0.4·VCC

IOL

Open load detection sink

current

Vout = VDG

100

A

tdf

Diagnostic detection filter time

for output 1 & 2 on each

diagnostic condition

s

Outputs timing

tdon1

Turn ON delay of OUT 1 and 2

NON1, 2 = 50% to VOUT = 0,9·Vbat

NCS = 50% to VOUT = 0,9·Vbat

(VBAT = 16V, RL = 500)

s

tdon2

Turn ON delay of OUT 3 to 8

NCS = 50% to VOUT = 0,9·Vbat

(VBAT = 16V, RL = 500)

s

tdoff

Turn OFF delay of OUT 1 to 8

NCS = 50% to VOUT = 0,1·Vbat

NON1, 2 = 50% to VOUT = 0,1·Vbat

(VBAT = 16V, RL = 500)

s

dUon1/dt Turn ON voltage slew-rate

For output 3 to 8; 90% to 30% of

Vbat; RL = 500; Vbat = 16V

0.7

3.5

s

dUon2/dt Turn ON voltage slew-rate

For output 1 and 2; 90% to 30%

of Vbat; RL = 500; Vbat = 16V

s

dUoff1/dt Turn OFF voltage slew-rate

For output 1 to 8; 30% to 90% of

Vbat; RL = 500; Vbat = 16V

s

dUoff2/dt Turn OFF voltage slew-rate

For output 1 to 8; 30% to 80% of

Vbat; RL = 500; Vbat = 0.9 · Vclp

s

Serial diagnostic link (load capacitor at SDO = 100 pF)

fclk

Clock frequency

50 % duty cycle

MHz

tclh

Minimum time CLK = high

160

tcll

Minimum time CLK = low

160

tpcld

Propagation delay CLK to data

at SDO valid

4.9 V

 V

CC  5.1V

100

Table 6.

Electrical characteristics (continued)

Symbol

Parameter

Test condition

Min.

Typ.

Max.

Unit

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