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L9969X Datasheet(PDF) 53 Page - STMicroelectronics |
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L9969X Datasheet(HTML) 53 Page - STMicroelectronics |
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53 / 70 page ![]() Symbol Parameter Condition Min Typ Max Unit Pin SO - Tristate output of the H-bridge. On active reset (VDD < VDD_POR) output SO is in tristate) In case of small current, resistive behavior can be assumed - - - - - VSO_L output low level I_SO = 2 mA 0.0 - 0.4 V VSO_H output high level I_SO = -2 mA VDD -0.5 - VDD V trf Rise/fall times (10% to 90%) CL = 25 pF CL = 100 pF CL = 200 pF 8 20 38 - 22 50 82 ns ISO Leakage current 0 < VSO < VDD -10 - 10 µA ISO Leakage current VDD < VSO < 18 V SO in tri- state mode 600 800 1000 µA CSO Capacity of SO in tristate - - - 10 pF Disturbance of SPI interface ∆Vx_L ∆Vx_H Change of input low or high level of SPI input pins in case of inverse current on VS - -0.1 - 0.1 V ∆ISx Change of input current of SPI input pins in case of inverse current on VS - -100 - 100 µA ∆ISO Change of leakage current of SPI output pin in case of inverse current on VS - -100 - 100 µA Table 42. SPI timing parameters Symbol Parameter Condition Min Typ Max Unit fs Baud Rate - - - 2 Mbit/s tcyc 1 - Cycle Time (referred to master) - 490 - - ns tlead 2 - Enable Lead Time (referred to master) - 50 - - ns tlag 3 - Enable Lag Time (referred to master) - 150 - - ns tv 4 - Data Valid (referred to master) CL = 25 pF CL = 100 pF CL = 200 pF - - 90 110 150 ns tsu 5 - Data Setup Time (referred to master) - 40 - - ns th 6 - Data Hold Time (referred to master) - 40 - - ns tdis 7 - Disable Time (referred to the H-bridge) - - - 100 ns tdt 8 - Transfer Delay (referred to master) - 250 - - ns tdld 9 - Disable Lead Time (referred to master) - 250 - - ns tdlg 10 - Disable Lag Time (referred to master) - 250 - - ns tacc 11 - Access Time (referred to master) - 8.35 - - µs L9969x Functional description DS14029 - Rev 6 page 53/70 |
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