VN9D30Q100F datasheet(13/98 Pages) STMICROELECTRONICS

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In sleep mode 2 the following limitations must be considered:

•

The diagnostics is not available.

•

The output stages are all off.

•

Protections are inactive.

The device enters sleep mode 2 under one condition:

•

If from standby mode, all direct inputs DIx are going low.

The device exits sleep mode 2 under three conditions:

•

If VDD falls below VDD_POR_OFF, the device enters reset mode.

•

If CSN is low for t > tstdby_out, the device enters fail-safe mode.

•

If one of the inputs DIx is set to 1, the device enters standby mode.

2.2.8

Battery undervoltage mode

This is not an operation mode but a transition step, where the power supply voltage is (VCC < VUSD).

If the battery supply voltage VCC falls below the undervoltage shutdown threshold (VCC < VUSD) the device enters

battery undervoltage mode.

The current sense diagnostic is not available.

The output stages are off regardless of SPI status or DIx.

Three different cases occur, depending on the operating mode:

1. From normal mode and from fail-safe mode:

In this mode, the digital supply voltage VDD is available (VDD > VDD_POR_ON). The SPI is active and read/write

functions are possible. The SPI diagnostics is available. After entering to the undervoltage mode, the

information about the undervoltage is saved in a flag (VCCUV) in the OUTSRx register, the SPI register

contents are retained. The SPI register reading is always possible.

If VCC rises above the threshold (VUSD + VUSDhyst) the device returns to the last mode and the flag is cleared

(VCCUV).

If during this state VDD decreases to VDD < VDD_POR_OFF, the device is reset completely. The last operation

mode information is lost. The device logic part is unpowered, therefore after increasing the supply voltage to

(VCC > VUSD + VUSDhyst) the operation mode is reset mode.

If during this state, the DIx is changed, the operation mode is not changed and the output state is changed

accordingly after VCC recovering.

2. From standby and sleep mode 2 modes:

In this mode, the digital supply voltage VDD is available (VDD > VDD_POR_ON). The SPI is not active and the

registers are frozen. The SPI diagnostics is not available. After entering to the undervoltage mode, the

information about the undervoltage is not saved in a flag (VCCUV).

If VCC rises above the threshold (VUSD + VUSDhyst) the device returns to the last mode.

If during this state (undervoltage mode) VDD decreases to VDD < VDD_POR_OFF, the device is reset completely.

The last operation mode information is lost. The device logic part is unpowered, therefore after increasing the

supply voltage to (VCC > VUSD + VUSDhyst) the operation mode is reset mode.

If during this state (under voltage mode) the DIx is changed, the operation mode is also changed. After VCC

recovering, this new operation mode is taken into account.

3. From reset mode or sleep mode1:

In this mode, the digital supply voltage VDD is not available (VDD < VDD_POR_OFF) and SPI is not active. It is

not possible to read/write via SPI. All SPI registers have the reset values. After entering to the undervoltage

mode, the information about the undervoltage is not saved in a flag (VCCUV).

If VCC rises above the threshold VUSD + VUSDhyst, the device returns to the last mode.

If during this state VDD increases to VDD > VDD_POR_ON, the device is completely reset. After VCC recovering

(VCC > VUSD + VUSDhyst), there will be a startup transition.

The undervoltage flag (VCCUV) is not saved in the following operation modes:

•

Reset mode,

•

Sleep mode 1,

•

Sleep mode 2,

•

Standby mode.

VN9D30Q100F

Functional description

DS13246 - Rev 9

page 13/98

VN9D30Q100F Datasheet(PDF) 13 Page - STMicroelectronics

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