Electronic Components Datasheet Search
  New Zealand  ▼
ALLDATASHEET.CO.NZ

X  

Preview PDF HTML

VNQ6004SATR-E Datasheet(PDF) 39 Page - STMicroelectronics

Part # VNQ6004SATR-E
Description  Quad-channel high-side driver with 16-bit SPI interface
PDF  73 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

VNQ6004SATR-E Datasheet(HTML) 39 Page - STMicroelectronics

Back Button VNQ6004SATR-E Datasheet HTML 35Page - STMicroelectronics VNQ6004SATR-E Datasheet HTML 36Page - STMicroelectronics VNQ6004SATR-E Datasheet HTML 37Page - STMicroelectronics VNQ6004SATR-E Datasheet HTML 38Page - STMicroelectronics VNQ6004SATR-E Datasheet HTML 39Page - STMicroelectronics VNQ6004SATR-E Datasheet HTML 40Page - STMicroelectronics VNQ6004SATR-E Datasheet HTML 41Page - STMicroelectronics VNQ6004SATR-E Datasheet HTML 42Page - STMicroelectronics VNQ6004SATR-E Datasheet HTML 43Page - STMicroelectronics Next Button
Zoom Inzoom in Zoom Outzoom out
 39 / 73 page
background image
DocID022315 Rev 5
39/73
VNQ6004SA-E
SPI functional description
72
3.3.12
Address 18h - 1Ah - Phase Control Register (PHASEXCR)
There are four Phase Control Registers, one for each output channel:
•
Address 18h - Phase Control Register of Channel 0 (PHASE0CR)
•
Address 19h - Phase Control Register of Channel 1 (PHASE1CR)
•
Address 1Ah - Phase Control Register of Channel 2 (PHASE2CR)
•
Address 1Bh - Phase Control Register of Channel 3 (PHASE3CR)
3.3.13
Address 2Eh - Channel Read Back Status Register (CHDRVR)
0
DUTYXCR0
R/W
0
0
1
0
...
...
0
1
Resulting Duty Cycle
...
...
Table 29. DUTYCXCR - duty cycle control register (continued)
Bit
Name
Access Reset
Content
0
256
----------
1
256
----------
2
256
----------
254
256
----------
255
256
----------
Table 30. PHASECXCR - duty cycle control register
Bit
Name
Access Reset
Content
7
PHASEXCR4
R/W
0
0
0
0
...
...
1
1
6
PHASEXCR3
R/W
0
0
0
0
...
...
1
1
5
PHASEXCR2
R/W
0
0
0
0
...
...
1
1
4
PHASEXCR1
R/W
0
0
0
1
...
...
1
1
3
PHASEXCR0
R/W
0
0
1
0
...
...
0
1
2
0
Reserved (not used): read as 0 and write to 0
1
0
Reserved (not used): read as 0 and write to 0
0
0
Reserved (not used): read as 0 and write to 0
Resulting Phase
...
...
0
32
------
1
32
------
2
32
------
30
32
------
31
32
------
Table 31. Channel read back status register
Bit
Name
Access
Reset
Content
70
Reserved
60
50
40
3
CHRBSR3
R
0
The CHDRVR allows to read back the actual state of each
channel.
1: channel OUTPUTX is on
0: channel OUTPUTX is off
2
CHRBSR2
R
0
1
CHRBSR1
R
0
0
CHRBSR0
R
0



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com