SPC574K70E7 datasheet(13/160 Pages) STMICROELECTRONICS

13 / 160 page

Figure 1. Block diagram

Calibration

Interface

LFAST

SPU

DCI

JTAGC

JTAGM

Nexus Aurora Router

SRAM

64 KB

Scaler

SP-FPU

I-Cache

Control

D-Cache

Control

VLE

I-Mem

Control

D-MEM

Control

Scaler

SP-FPU

VLE

I-Mem

Control

D-MEM

Control

4KB

2 way

2KB

2 way

16KB

I-MEM

64KB

D-MEM

Ethernet

FlexRay

Zipwire

(LFAST

&SIPI)

Unified

Backdoor

Interface

with

E2E ECC

16 KB

I-MEM

48 KB

D-MEM

SWT_2

SRAM Control

with E2E ECC

Decorated

Access

Core Memory Protection Unit

(CMPU)

Core Memory Protection Unit

(CMPU)

Peripheral Domain– 40MHz

Computational Shell– Fast Domain160 MHz

Overlay

Backdoor for

System RAM

FLASH

2.5 MB

EEPROM

4x16KB

NVM (Single Module)

256 Page Line

Buddy Device Interface

Dual INTC

E200 z420– 160 MHz

Main Core_0

Nexus3p

BIU with E2E ECC

STM_0

SWT_0

32 ADD

64 DATA

Instruction

32ADD

64DATA

Load/

Store

Fast Cross Bar Switch (XBAR_0, AMBA2.0 v6 AHB) – 64 bit– 160 MHz

System Memory Protection Unit(SMPU_0)

32 ADD

64 DATA

32 ADD

64 DATA

32 ADD

64 DATA

E200z225 – 80MHz

Peripheral Core_2

Nexus3p

BIU with E2E ECC

STM_2

Instruction

32 ADD

64 DATA

Load/

Store

Slow Cross Bar Switch (XBAR_1, AMBA2.0 v6AHB) – 32 bit– 80 MHz

System Memory Protection Unit(SMPU_1)

32 ADD

32 DATA

Intelligent

Bridging

Bus Gasket

Peripheral Bridge A

E2E ECC

Decorate Storage

40 MHz

Peripheral Cluster A

(See “Periphery

allocation” diagram )

Peripheral Cluster B

(See“Periphery

allocation” diagram )

Concentrator

With

E2E ECC

40 MHz

Nexus Data

Trace

Concentrator

With

E2E ECC

80 MHz

Nexus Data

Trace

32ch. eDMA

with E2E ECC

DMAMUX

Peripherals

allocation to

the bridges

is based on

safety and

pinout

requirements

Delayed Lock-step

with Redundancy

Checkers

LSP

ScalerSP-

FPU

I-Cache

Control

D-Cache

Control

VLE

I-Mem

Control

D-MEM

Control

Unified

Backdoor

Interface

With

E2E ECC

Core Memory Protection Unit

(CMPU)

E200z419 – 160 MHz

Checker Core_0s

BIU with E2E ECC

Safety Lake

FLASH Controller

Dual Ported Incl.

Set-Associative

Prefetch Buffers

with E2E ECC

Peripheral Bridge B

E2E ECC

Decorate Storage

40 MHz

Unified

Backdoor

Interface

with

E2E ECC

Overlay RAM

16 KB

32 ADD

32 DATA

32ADD

32DATA

32ADD

32DATA

32 ADD

32 DATA

SWT_3

Delay

RCCU

Delay

SPC574K70E7 Datasheet(PDF) 13 Page - STMicroelectronics

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