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STM32L443CC Datasheet(PDF) 118 Page - STMicroelectronics

Part # STM32L443CC
Description  Ultra-low-power Arm® Cortex®-M4 32-bit MCUFPU, 100DMIPS, 256KB Flash, 64KB SRAM, USB FS, LCD, analog, audio, AES
PDF  215 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32L443CC Datasheet(HTML) 118 Page - STMicroelectronics

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Electrical characteristics
STM32L443CC STM32L443RC STM32L443VC
118/215
DS11421 Rev 4
6.3.6
Wakeup time from low-power modes and voltage scaling
transition times
The wakeup times given in Table 40 are the latency between the event and the execution of
the first user instruction.
The device goes in low-power mode after the WFE (Wait For Event) instruction.
APB1
USART3 independent clock
domain
4.3
3.5
4.2
µA/MHz
USART3 clock domain
1.5
1.1
1.3
WWDG
0.5
0.5
0.5
All APB1 on
51.5
35.5
48.6
APB2
AHB to APB2(4)
1.0
0.9
0.9
FW
0.2
0.2
0.2
SAI1 independent clock domain
2.3
1.8
1.9
SAI1 clock domain
2.1
1.8
2.0
SDMMC1 independent clock
domain
4.7
3.9
3.9
SDMMC1 clock domain
2.5
1.9
1.9
SPI1
1.8
1.6
1.7
SYSCFG/VREFBUF/COMP
0.6
0.5
0.6
TIM1
8.1
6.5
7.6
TIM15
3.7
3.0
3.4
TIM16
2.7
2.1
2.6
USART1 independent clock
domain
4.8
4.2
4.6
USART1 clock domain
1.5
1.3
1.7
All APB2 on
24.2
19.9
22.6
ALL
100.9
77.1
94.8
1. The BusMatrix is automatically active when at least one master is ON (CPU, DMA).
2. The GPIOx (x= A…H) dynamic current consumption is approximately divided by a factor two versus this table values when
the GPIO port is locked thanks to LCKK and LCKy bits in the GPIOx_LCKR register. In order to save the full GPIOx current
consumption, the GPIOx clock should be disabled in the RCC when all port I/Os are used in alternate function or analog
mode (clock is only required to read or write into GPIO registers, and is not used in AF or analog modes).
3. The AHB to APB1 Bridge is automatically active when at least one peripheral is ON on the APB1.
4. The AHB to APB2 Bridge is automatically active when at least one peripheral is ON on the APB2.
Table 39. Peripheral current consumption (continued)
Peripheral
Range 1
Range 2
Low-power run
and sleep
Unit



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