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STM32L443CC Datasheet(PDF) 175 Page - STMicroelectronics |
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STM32L443CC Datasheet(HTML) 175 Page - STMicroelectronics |
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175 / 215 page  DS11421 Rev 4 175/215 STM32L443CC STM32L443RC STM32L443VC Electrical characteristics 185 Figure 33. SPI timing diagram - slave mode and CPHA = 0 tv(SO) Data output valid time Slave mode 2.7 < VDD < 3.6 V Voltage Range 1 - 12.5 13.5 ns Slave mode 1.71 < VDD < 3.6 V Voltage Range 1 -12.5 24 Slave mode 1.71 < VDD < 3.6 V Voltage Range 2 -12.5 33 tv(MO) Master mode - 4.5 6 th(SO) Data output hold time Slave mode 7 - - ns th(MO) Master mode 0 - - 1. Guaranteed by characterization results. 2. Maximum frequency in Slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit into SCK low or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master having tsu(MI) = 0 while Duty(SCK) = 50 %. Table 84. SPI characteristics(1) (continued) Symbol Parameter Conditions Min Typ Max Unit |
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