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ICS932S422C Datasheet(PDF) 13 Page - Integrated Circuit Systems |
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ICS932S422C Datasheet(HTML) 13 Page - Integrated Circuit Systems |
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13 / 21 page ![]() 13 Integrated Circuit Systems, Inc. ICS932S422C 1412A—12/10/07 SMBus Table: Byte Count Register Pin # Name Control Function Type 0 1 PWD Bit 7 BC7 RW 0 Bit 6 BC6 RW 0 Bit 5 BC5 RW 0 Bit 4 BC4 RW 0 Bit 3 BC3 RW 1 Bit 2 BC2 RW 0 Bit 1 BC1 RW 0 Bit 0 BC0 RW 0 SMBus Table: Device ID Register Pin # Name Control Function Type 0 1 PWD Bit 7 DID7 R - - 0 Bit 6 DID6 R - - 0 Bit 5 DID5 R - - 0 Bit 4 DID4 R - - 0 Bit 3 DID3 R - - 1 Bit 2 DID2 R - - 1 Bit 1 DID1 R - - 0 Bit 0 DID0 R - - 0 SMBus Table: M/N Programming & Control Register Pin # Name Control Function Type 0 1 PWD Bit 7 M/N_EN CPU and SRC M/N Programming RW Disable Enable 0 Bit 6 0 Bit 5 Spread Spectrum Enable Spread Off/On RW Spread Off Spread On 0 Bit 4 Spread Spectrum Enable Spread Off/On RW Spread Off Spread On 0 Bit 3 SRC Alternate Frequency (96% of Nominal) Set SRC = 96 MHz and PCI = 32 MHz Only active if Byte 10, bit 2 = 1 RW Normal Alternate Frequency 0 Bit 2 CPU Alternate Frequency (96% of Nominal) Only active if latched frequency is 166 MHz or 333 MHz. Set alternate CPU frequency: 166 MHz to 160 MHz 333 MHz to 320 MHz RW Normal Alternate Frequency 0 Bit 1 REF1 Drive Strength 1X or 2X RW 1 Bit 0 REF0 Drive Strength 1X or 2X RW 1 Byte Count Programming b(7:0) Writing to this register will configure how many bytes will be read back, default is 8 bytes. (0 to 7) - - - - - - Byte 8 Byte 9 - - 55 - - CPU SRC CPU 54 See REF Drive Strength Functionality Table SRC, PCI Device ID (0C hex) RESERVED Byte 10 |
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