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ICSXXXXYGLFT Datasheet(PDF) 2 Page - Integrated Circuit Systems |
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ICSXXXXYGLFT Datasheet(HTML) 2 Page - Integrated Circuit Systems |
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2 / 20 page ![]() 2 ICS932S825 1276D—10/25/07 Pin Description PIN # PIN NAME TYPE DESCRIPTION 1 X1 IN Crystal input, Nominally 14.318MHz. 2 X2 OUT Crystal output, Nominally 14.318MHz 3 VDDREF_STB PWR Ref, XTAL power supply, nominal 3.3V standby power 4 REF0_RUN_2x OUT 14.318MHz Free Running XTAL Output. This output runs as long as standby VDD is applied to the part. Default drive is 2 loads. 5 FS1/REF1_2x I/O Frequency select latch input pin / 14.318 MHz reference clock. Default 2 load drive. 6 FS2/REF2_2x I/O Frequency select latch input pin / 14.318 MHz reference clock. Default 2 load drive. 7 GNDREF PWR Ground pin for the REF outputs. 8 VDD48 PWR Power pin for the 48MHz output.3.3V 9 48MHz_0_2x OUT 48MHz clock output. Default 2 load drive strength 10 48MHz_1_2x OUT 48MHz clock output. Default 2 load drive strength 11 GND48 PWR Ground pin for the 48MHz outputs 12 SCLK IN Clock pin of SMBus circuitry, 5V tolerant. 13 SDATA I/O Data pin for SMBus circuitry, 3.3V tolerant. 14 VDDPCI PWR Power supply for PCI clocks, nominal 3.3V 15 PCICLK0_2x OUT 3.3V PCI clock output. Default 2 load drive strength. 16 PCICLK1_2x OUT 3.3V PCI clock output. Default 2 load drive strength. 17 GNDPCI PWR Ground pin for the PCI outputs 18 CLKPWRGD/PD# IN This 3.3V LVTTL input is a level sensitive strobe used to determine when latch inputs are valid and are ready to be sampled. This is an active high input. / Asynchronous active low input pin used to power down the device into a low power state. 19 GND PWR Ground pin. 20 VDDA PWR 3.3V power for the PLL core. 21 GNDA PWR Ground pin for the PLL core. 22 GND PWR Ground pin. 23 PCIeT_L0 OUT True clock of 0.8V differential push-pull PCI_Express pair (no 50ohm resistor to GND needed) 24 PCIeC_L0 OUT Complement clock of 0.8V differential push-pull PCI_Express pair. (no 50ohm resistor to GND needed) 25 PCIeT_L1 OUT True clock of 0.8V differential push-pull PCI_Express pair (no 50ohm resistor to GND needed) 26 PCIeC_L1 OUT Complement clock of 0.8V differential push-pull PCI_Express pair. (no 50ohm resistor to GND needed) 27 GND PWR Ground pin. 28 VDDPCIe PWR Power supply for PCI Express clocks, nominal 3.3V 29 PCIeT_L2 OUT True clock of 0.8V differential push-pull PCI_Express pair (no 50ohm resistor to GND needed) 30 PCIeC_L2 OUT Complement clock of 0.8V differential push-pull PCI_Express pair. (no 50ohm resistor to GND needed) 31 PCIeT_L3 OUT True clock of 0.8V differential push-pull PCI_Express pair (no 50ohm resistor to GND needed) 32 PCIeC_L3 OUT Complement clock of 0.8V differential push-pull PCI_Express pair. (no 50ohm resistor to GND needed) |
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