I/O(2)

28-Pin

SPDIP,

SOIC,

SSOP

28-Pin

(U)QFN

A/D

Reference Comparator Timers

CCP

CWG

ZCD Interrupt EUSART

DSM

MSSP

Pull-

up

Basic

VSS

8

5

—

—

—

—

—

—

—

—

—

—

—

—

VSS

OUT(2)

—

—

ADGRDA

ADGRDB

—

C1OUT

C2OUT

TMR0

CCP1

CCP2

PWM3

PWM4

CWG1A

CWG1B

CWG1C

CWG1D

—

—

TX1/

CK1(3)

DT1(3)

DSM

SDO1

SCK1

—

—

Note: 

1.

This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins. Refer to the

peripheral input selection table for details on which PORT pins may be used for this signal.

2.

All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin options as described in the

peripheral output selection table.

3.

This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers.

4.

These pins are configured for I2C logic levels; The SCLx/SDAx signals may be assigned to any of these pins. PPS assignments to the other pins (e.g., RB1) will

operate, but input logic levels will be standard TTL/ST as selected by the INLVL register, instead of the I2C specific or SMBus input buffer thresholds.

Table 2.  40/44-Pin Allocation Table

I/O(2)

40-

Pin

PDIP

40-

Pin

UQFN

44-

Pin

QFN

44-

Pin

TQFP

A/D

Reference Comparator Timers

CCP

CWG

ZCD Interrupt EUSART

DSM

MSSP

Pull-

up

Basic

RA0

2

17

19

19

ANA0

—

C1INO-

C2IN0-

—

—

—

—

IOCA0

—

—

—

Y

—

RA1

3

18

20

20

ANA1

—

C1IN1-

C2IN1-

—

—

—

—

IOCA1

—

—

—

Y

—

RA2

4

19

21

21

ANA2

DAC1OUT1

Vref-

(DAC5)

Vref- (ADC)

C1IN0+

C2IN0+

—

—

—

—

IOCA2

—

—

—

Y

—

RA3

5

20

22

22

ANA3

Vref+

(DAC5)

Vref+

(ADC)

C1IN1+

—

—

—

—

IOCA3

—

MDCIN1(1)

—

Y

—

RA4

6

21

23

23

ANA4

—

—

T0CKI(1)

—

—

—

IOCA4

—

MDCIN2(1)

—

Y

—

RA5

7

22

24

24

ANA5

—

—

—

—

—

—

IOCA5

—

MDMIN(1)

SS1(1)

Y

—

RA6

14

29

33

31

ANA6

—

—

—

—

—

—

IOCA6

—

—

—

Y

CLKOUT

OSC2

RA7

13

28

32

30

ANA7

—

—

—

—

—

—

IOCA7

—

—

—

Y

OSC1

CLKIN

RB0

33

8

9

8

ANB0

—

C2IN1+

—

—

CWG1(1) ZCDIN IOCB0

INT0(1)

—

—

SS2(1)

Y

—

RB1

34

9

10

9

ANB1

—

C1IN3-

C2IN3-

—

—

—

—

IOCB1

INT1(1)

—

—

SCK2(1)

SCL2(3,4)

Y

—

RB2

35

10

11

10

ANB2

—

—

—

—

—

—

IOCB2

INT2(1)

—

—

SDI2(1)

SDA2(3,4)

Y

—

RB3

36

11

12

11

ANB3

—

C1IN2-

C2IN2-

—

—

—

—

IOCB3

—

—

—

Y

—

RB4

37

12

14

14

ANB4

—

—

T5G(1)

—

—

—

IOCB4

—

—

—

Y

—

RB5

38

13

15

15

ANB5

—

—

T1G(1)

—

—

—

IOCB5

—

—

—

Y

—

RB6

39

14

16

16

ANB6

—

—

—

—

—

—

IOCB6 CK2(1,3)

—

—

Y

ICSPCLK

PIC18F2X/4XQ10

© 2017 Microchip Technology Inc.

Product Brief

DS40001920A-page 9